Computational lithography has been playing a critical role in enabling the semiconductor industry. After source mask co-optimization (SMO), inverse lithography has become the ultimate frontier of computational lithography. Full chip implementation of rigorous inverse lithography remains impractical because of enormous computational hardware resource requirements and long computational time, the situation exacerbates for EUV computational lithography where mask 3D effect is more pronounced. One very promising technique to overcome the barrier is to take full advantage of the maturing machine learning techniques based on neural network architecture. Some success has been achieved using deep convolution neural network (DCNN) to obtain inverse lithography technology (ILT) solution with significantly less computational time. In DCNN, to extract features with sufficient resolution and nearly complete representation, the feature extract layers are very complicated and lack of physical meaning. More importantly, the training requires large number of well balanced samples, which makes the training more difficult and time consuming. To alleviate the difficulties relating to DCNN, we have proposed the physics based optimal feature vector design for machine learning based computational lithography. The innovative physics based feature vector design eliminates the need of feature extraction layers in neural network, only layers for mapping function construction are needed, which greatly reduces the NN training time and accelerates the NN model SRAF generation for full chip. In this paper, we will present our machine learning based inverse lithography results with adaptive and dynamical sampling scheme for neural network training.
The semiconductor design node shrinking requires tighter edge placement errors (EPE) budget. OPC error, as one major contributor of EPE budget, need to be reduced with better OPC model accuracy. In addition, the CD (Critical Dimension) shrinkage in advanced node heavily relies on the etch process. Therefore AEI (After Etch Inspection) metrology and modeling are important to provide accurate pattern correction and optimization. For nodes under 14nm, the etch bias (i.e. the bias between ADI (After Development Inspection) CD and AEI CD) could be -10 nm ~ -50 nm, with a strong loading and aspect-ratio dependency. Etch behavior in advanced node is very complicated and brings challenges to conventional rule based OPC correction. Therefore, accurate etch modeling becomes more and more important to make precise prediction of final complex shapes on wafer for OPC correction. In order to ensure the accuracy of etch modeling, high quality metrology is necessary to reduce random error and systematic measurement error. Moreover, CD gauges alone are not sufficient to capture all the effects of the etch process on different patterns. Edge placement (EP) gauges that accurately describe the contour shapes at various key positions are needed. In this work we used the AEI SEM images obtained from traditional CD-SEM flow, processed with ASML’s MXP (Metrology for eXtreme Performance) tool, and used the extracted CD gauges and massive EP gauges to train a deeplearning Newron Etch model. In the approach, MXP reduced the AEI metrology random errors and shape fitting measurement error and provides better pattern coverage with massive reliable CD and EP gauges, Newron Etch captures complex and unknown physical and chemical effects learned from wafer data. Results shows that MXP successfully extracted stable contour from AEI SEM for various pattern types. Three etch models are calibrated and compared: CD based EEB model (Effective Etch Bias), CD+EP based EEB model, and CD+EP based Newron etch model. CD based EEB model captures the major trend of the etch process. Including EP gauges helps EEB model with about 10% RMS reduction on prediction. Integration of MXP (CD+EP) and Newron Etch model gains about 45% prediction RMS reduction compared to baseline model. The good prediction of Newron Etch is also verified from wafer SEM overlay on complex-shape patterns. This result validates the effectiveness of ASML’s solution of deep learning etch model integration with MXP AEI’s massive wafer data extraction from etch process, and will help to provide accurate and reliable etch modeling for advanced node etch OPC correction in semiconductor manufacturing.
The semiconductor manufacturing roadmap which generally follows Moore’s law requires smaller and smaller EPE (Edge Placement Error), and this places stricter requirements on OPC model accuracy, which is mainly limited by metrology errors, pattern coverage and model form. Current metrology errors are mainly related to SEM image noise and measurement difficulty in complex 2D patterns. And traditional model form improvement by adding empirical terms for PEB (Post Exposure Bake), NTD (Negative Tone Development) and PRS (Physical Resist Shrinkage) effects still cannot meet the accuracy spec because other physical and chemical effects are uncaptured. Fitting these effects also requires comprehensive pattern coverage during model calibration. Solely improving model form may overfit the metrology error, which is risky, while solely improving metrology ignores existing model errors: both factors are troublesome for OPC. In this paper, a new metrology (MXP, naming for Metrology of Extreme Performance) and deep learning (Newron, naming for a Deep Convolutional Neural Network model form) integrated solution is proposed, where MXP decreases the metrology errors and provides good pattern coverage with high-volume reliable CD and EP (Edge Placement) gauges, and Newron captures remaining complex physical and chemical effects embedded in high-volume gauges beyond the traditional model. This solution shows overall ~30% prediction accuracy improvement compared to baseline metrology and FEM+ (Focus Exposure Matrix) model flow in N14 NTD process, predicts SEM shape of critical weak points more accurately.
With semiconductor technology progressing beyond 5nm node, there is tremendous pressure on computational lithography to achieve both accuracy and speed. One very promising technique to accomplish this mission is to take full advantage of the maturing machine learning techniques based on neural network architecture. Some success has been achieved using convolution neural network (CNN) to obtain inverse lithography technology (ILT) solution with significantly less computational time. In general, CNN architecture consists of feature extraction layers and nonlinear mapping function construction layers. To train a CNN model requires a large amount of data and computational resource. To maintain certain intrinsic symmetries of imaging behavior, the feature extraction layers must be carefully engineered using weight sharing techniques or using well balanced training samples of different orientations, otherwise, feature extraction part will be skewed. It is therefore very desired to have a scheme that can obtain optimal feature vector for machine learning based computational lithography automatically without the need of feature extraction layers in CNN. In this paper, we will make an attempt to describe such a scheme and present our test results on machine learning based OPC and ILT solution. It should be understood that machine learning based computational lithography solutions do not possess the capability to replace conventional OPC or ILT completely due to its lack of required accuracy. However, it can provide an initial solution that is close enough to final OPC solution or ILT solution, therefore fast OPC and fast ILT can be realized.