The control of edge placement error (EPE) is playing key role in the patterning of advanced technology node in semiconductor industry. EPE is evaluated by the metric of overlay, distance of patterns between two layers in multi patterning, and patterning error in local area. In past instance, overlay between upper layer and underlayer was measured by electron beam (e-beam) metrology system with scanning electron microscopy (SEM) image. <p> </p>EPE which is caused by local patterning error on photoresist layer is influenced by scanner tool parameters such as focus and exposure. Technology and method of EPE measurement on photoresist layer is highly required to optimize scanner tool performance. <p> </p>This study provides the measurement method of EPE on photoresist layer resulting from variation of scanner tool condition. Definition of EPE in this study is the distance between contour of SEM pattern and contour of target layout. Die to Database (D2DB) technology which compares image and layout data was applied to this study with large image size which include huge number of patterns. The advantage of the method was confirmed by the experiment on the verification of local patterning error. <p> </p>The result of the experiment shows scanner tool conditions are well represented by these local patterning errors. In addition, optimizing scanner parameters and monitoring scanner condition by these local patterning errors are proposed.
Up until now, the main driving force for the semiconductor industry is the continual shrinkage of device feature sizes, thereby incorporating more devices per unit area, reducing manufacturing cost and enhancing their performance have been achieved. However, the shrinkage of feature size leads to a reduction of process window imposing an extremely tight requirement for parameters such as critical dimension (CD), edge and width roughness of spaces/trenches, contacts, lines, and tip to tip (T2T) values. At sub 14 nm technology nodes these parameters have a significant influence on the overall device performance. With EUV based pattering becoming the sole option at these advanced nodes, a thorough characterization of the patterning process is of utmost importance before it can be a high-volume manufacturing solution.<p> </p> In this work, we show how e-beam inspection has been used to characterize a single exposure EUV M2 (Metal 2 layer, BEoL) to have an understanding of the different hotspots and intra-field signatures present. Design Based Metrology (DBM) with wide SEM image was employed to measure CD distribution and Edge Placement Error (EPE) distribution of metal layer pattern on the 10nm logic wafer.
To reduce charging and shrinkage, CD-SEMs utilize low electron energies and multiframe imaging. This results in every next frame being altered due to stage and beam instability, as well as due to charging. Regular averaging of the frames blurs the edges; this directly effects the extracted values of critical dimensions. A technique was developed to overlay multiframe images without the loss of quality. This method takes into account drift, rotation, and magnification corrections, as well as nonlinear distortions due to wafer charging. A significant improvement in the signal to noise ratio and overall image quality without degradation of the feature’s edge quality was achieved. The developed software is capable of working with regular and large size images up to 32K pixels in each direction.
Severe process margin in advanced technology node of semiconductor device is controlled by e-beam metrology system and e-beam inspection system with scanning electron microscopy (SEM) image. By using SEM, larger area image with higher image quality is required to collect massive amount of data for metrology and to detect defect in a large area for inspection. Although photoresist is the one of the critical process in semiconductor device manufacturing, observing photoresist pattern by SEM image is crucial and troublesome especially in the case of large image. The charging effect by e-beam irradiation on photoresist pattern causes deterioration of image quality, and it affect CD variation on metrology system and causes difficulties to continue defect inspection in a long time for a large area. In this study, we established a quantitative approach for optimizing e-beam condition with “Die to Database” algorithm of NGR3500 on photoresist pattern to minimize charging effect. And we enhanced the performance of measurement and inspection on photoresist pattern by using optimized e-beam condition. NGR3500 is the geometry verification system based on “Die to Database” algorithm which compares SEM image with design data . By comparing SEM image and design data, key performance indicator (KPI) of SEM image such as "Sharpness", "S/N", "Gray level variation in FOV", "Image shift" can be retrieved. These KPIs were analyzed with different e-beam conditions which consist of “Landing Energy”, “Probe Current”, “Scanning Speed” and “Scanning Method”, and the best e-beam condition could be achieved with maximum image quality, maximum scanning speed and minimum image shift. On this quantitative approach of optimizing e-beam condition, we could observe dependency of SEM condition on photoresist charging. By using optimized e-beam condition, measurement could be continued on photoresist pattern over 24 hours stably. KPIs of SEM image proved image quality during measurement and inspection was stabled enough.
The quality of patterns printed on wafer may be attributed to factors such as process window control, pattern fidelity, overlay performance, and metrology. Each of these factors play an important role in making the process more effective by ensuring that certain design- and process-specific parameters are kept within acceptable variation. Since chip size and pattern density are increasing accordingly, in-line real time catching the in-chip weak patterns/defects per million opportunities (WP-DPMO) plays more and more significant role for product yield with high density memory. However, the current in-line inspection tools focus on single layer defect inspection, not effectively and efficiently to catch multi-layer weak patterns/defects even through voltage contrast and/or special test structure design -. In general, the multi-layer weak patterns/defects are escaped easily by using in-line inspection and cause ignorance of product dysfunction until off-line time-consuming final PFA/EFA will be used. <p> </p>To effectively and efficiently in-line real time monitor the potential multi-layer weak patterns, we quantify the bridge electrical metric between contact and gate electrodes into CD physical metric via big data from the larger field of view (FOV: 8k x 16k with 3 nm pixel equalizes to image main field size 34 um x 34 um @ 3 nm pixel) e-beam quality image contour compared to layout GDS database (D2DB) as shown in Fig. 1. Hadoop-based distributed parallel computing is implemented to improve the performance of big data architectures, Fig. 2. Therefore, the state of art in-line real time catching in-chip potential multi-layer weak patterns can be proven and achieved by following some studying cases . Therefore, manufacturing sources of variations can be partitioned to systematic and random variations by applying statistical techniques based on the big data fundamental infrastructures. After big data handling, the in-chip CD and AA variations are distinguished by their spatial correlation distance. For local variations (LV) there is no correlation, whereas for global variations (GV) the correlation distance is very large -. This is the first time to certificate the validation of spatial distribution from the affordable bias contour big data fundamental infrastructures. And then apply statistical techniques to dig out the variation sources. The GV come from systematic issue, which could be compensated by adaptive LT condition or OPC correction. But LV comes from random issue, which being considered as intrinsic problem such as structure, material, tool capability… etc. <p> </p>In this paper studying, we can find out the advanced technology node SRAM contact CD local variation (LV) dominates in total variation, about 70%. It often plays significant in-line real time catching WP-DPMO role of the product yield loss, especially for wafer edge is the worst loss within wafer distribution and causes serious reliability concern. The major root cause of variations comes from the PR material induced burr defect (LV), the second one comes from GV enhanced wafer edge short opportunity, which being attributed to three factors, first one factor is wafer edge CD deliberated enlargement for yield improvement as shown in Fig. 10. Second factor is overlaps/AA shifts due to tool capability dealing with incoming wafer’s war page issue and optical periphery layout dependent working pitch issue as shown in Fig. 9 (1)., the last factor comes from wafer edge burr enhanced by wafer edge larger Photo Resistance (PR) spin centrifugal force. <p> </p>After implementing KPIs such as GV related AA/CD indexes as shown in Fig. 9 (1) and 10, respectively, and LV related burr index as shown in Fig. 11., we can construct the parts per million (PPM) level short probability model via multi-variables regression, canonical correlation analysis and logistic transformation. The model provides prediction of PPM level electrical failure by using in-line real time physical variation analysis. However in order to achieve Total Quality Management (TQM), the adaptive Statistical Process Control (SPC) charts can be implemented to in-line real time catch PPM level product malfunction at manufacturing stage. Applying for early stage monitor likes incoming raw material, Photo Resistance (PR) … etc., the LV related burr KPI SPC charts could be a powerful quality inspection vehicle. To sum up the paper’s contributions, the state of art in-line real time catching in-chip potential multi-layer physical weak patterns can be proven and achieved effectively and efficiently to associate with PPM level product dysfunction.