For 28 nm technology node and below resist profiles need to be taken in to consideration during optical proximity correction (OPC) and verification. The low k1 results in a shallower depth of focus and thus thinner resists, which combined with the process limits increases the risk of resist degradation. Only considering the resist critical dimensions at a single focal plane (such as at the bottom of the resist stack) will miss the impact of the resist 3D profile, like top loss or bottom footing, which can transfer to etch hard pattern failures. To date, modeling to study resist 3D profiles has been available using rigorous simulators and has been used as a verification method for hot spots captured during full chip OPC verification, but not for full chip verification due to the high computational run time cost. This paper demonstrates a 3D resist compact OPC model concept and implementation in a full chip OPC and verification flow. The results show significant improvement for full chip OPC quality with a good correlation between simulation and real wafer hot spots. Because resist profiles are not directly correlated to etch failure, the relationship between the resist profile and etch failures and how to characterize the threshold to dispose the hot spots for the 3D compact model was also investigated.
Due to the continuous shrinking in half pitch and critical dimension (CD) in wafer processing, maintaining a reasonable
process window such as depth of focus (DOF) & exposure latitude (EL) becomes very challenging. With the source
mask optimization (SMO) methodology, the lithography process window can be improved and a smaller mask error
enhancement factor (MEEF) can be achieved.
In this paper, the Tachyon SMO work flow and methodology was evaluated. The optimum source was achieved through
evaluation of the critical designs with Tachyon SMO software and the simulated performance was then verified on
another test case. Criteria such as DOF, EL & MEEF were used to determine the optimum source achieved from the
evaluation. Furthermore, the process variation band (PV-Band) and the number of hot spot (design weak points) were
compared between the POR and the optimum source. The simulation result shows the DOF, MEEF & worst PV-Band
were improved by 13%, 17% & 12%, respectively with the optimum SMO source.
In order to verify the improvement from the optimum SMO at the silicon level, a new OPC model was recalibrated with
wafer CD from the optimized source. The OPC recipe was also optimized and a reticle was retrofitted with the new OPC.
By comparing the process window, hotspots and defects between the original vs. new reticle, the benefit of the optimized
source was verified on silicon.