Extreme ultraviolet lithography (EUVL) systems struggle from both low source brightness and low source throughput through the tool. For these reasons, photon shot noise will play a much larger role in image process development for EUVL than in DUV processes. Furthermore, the lower photon count increases the stochastic variation of all the processes which occur after photon absorption. This causes the printed edge to move away from the mean edge with some probability. This paper will present a model form and calibration flow for including stochastic probability bands in compact models suitable for full chip simulation. This model form relies on calibrating to statistical data from a rigorous EUV stochastic lithography model calibrated to wafer experimental data. The data generation, data preparation, and model calibration flows for the compact stochastic probability bands will be presented. We will show that this model form can predict patterns which are prone to stochastic pattern failure in realistic mask designs, as well as how this model form can be used downstream for full chip correction (e.g., SMO, OPC and/or ILT).
Model-based optical proximity correction (MB-OPC) has been widely applied in advanced lithography processes today. As k1 factor decreases and circuit design complexity increases, various advanced OPC modeling techniques have been employed to better simulate the lithography processes, such as mask3D (M3D), negative tone development (NTD) modeling techniques, etc. These advanced OPC modeling techniques introduce increasingly nonlinear behaviors in MB-OPC and bring many challenges in controlling edge placement error (EPE) and critical dimension (CD) while maintaining non-aggressive mask correction where possible for mask-rule check (MRC) compliance and better yield. In this paper, we review the MB-OPC challenges, and show our integration of Proteus inverse lithography technology (ILT) with MB-OPC as the solution to these challenges.
EUV lithography is viewed as a highly desirable technology for 5nm and 7nm node patterning cost reduction and process simplicity. However, for the 5nm and 7nm nodes EUV not only needs to function in a low-K1 resolution environment but has several new and complex patterning issues which will need accurate compensation by mask synthesis tools and flows. The main new issues are: long-range flare variation across the chip, feature dependent focus offsets due to high mask topography, asymmetry inducing shadowing effects which vary across the lens slit, significantly higher lens aberrations, illumination source changes (across the lens and with time) and new resist exposure mechanisms. These solutions must be successfully deployed at low K1 values and must be integrated together to create OPC/RET flows which have high resolution, high accuracy, and are fast to deploy. Therefore, the combined requirements of low-K1 resolution, full reticle correction accuracy and process window can be even more challenging than in current optical lithography mask synthesis flows.
Advanced computational methods such as ILT and model-based SRAF optimization are well known to have considerable benefits in process window and resolution for low-K1 193 lithography. However, these methods have not been well studied to understand their benefits for lower-K1 EUV lithography where fabs must push EUV resolution, 2D accuracy and process window to their limits. In this paper, we investigate where inverse lithography methods can improve EUV patterning weaknesses vs. traditional OPC/RET. We first show how ILT can be used to guide a better understanding of optimal solutions for EUV mask synthesis. We then provide detailed comparisons of ILT and traditional methods on a wide range of mask synthesis applications.
Traditional segment-based model-based OPC methods have been the mainstream mask layout optimization techniques in volume production for memory and embedded memory devices for many device generations. These techniques have been continually optimized over time to meet the ever increasing difficulties of memory and memory periphery patterning. There are a range of difficult issues for patterning embedded memories successfully. These difficulties include the need for a very high level of symmetry and consistency (both within memory cells themselves and between cells) due to circuit effects such as noise margin requirements in SRAMs. Memory cells and access structures consume a large percentage of area in embedded devices so there is a very high return from shrinking the cell area as much as possible. This aggressive scaling leads to very difficult resolution, 2D CD control and process window requirements. Additionally, the range of interactions between mask synthesis corrections of neighboring areas can extend well beyond the size of the memory cell, making it difficult to fully take advantage of the inherent designed cell hierarchy in mask pattern optimization. This is especially true for non-traditional (i.e., less dependent on geometric rule) OPC/RET methods such as inverse lithography techniques (ILT) which inherently have more model-based decisions in their optimizations. New inverse methods such as model-based SRAF placement and ILT are, however, well known to have considerable benefits in finding flexible mask pattern solutions to improve process window, improve 2D CD control, and improve resolution in ultra-dense memory patterns. They also are known to reduce recipe complexity and provide native MRC compliant mask pattern solutions. Unfortunately, ILT is also known to be several times slower than traditional OPC methods due to the increased computational lithographic optimizations it performs. In this paper, we describe and present results for a methodology to greatly improve the ability of ILT to optimize advanced embedded memory designs while retaining significant hierarchy and cell design symmetry, therefore, have good turnaround time and CD uniformity. This paper will explain the enhancements which have been developed in order to overcome the traditional difficulties listed above. These enhancements are in the categories of local CD control, global chip processing options, process window benefit, turn-around time and hierarchy retention.
As the industry pushes to ever more complex illumination schemes to increase resolution for next generation memory
and logic circuits; subresolution assist feature (SRAF) placement requirements become increasingly severe. Therefore
device manufacturers are evaluating improvements in SRAF placement algorithms which do not sacrifice main feature
(MF) patterning capability. AF placement algorithms can be categorized broadly as either rule-based (RB), model-based
(MB). However, combining these different algorithms into new integrated solutions may enable a more optimal overall
RBAF is the baseline AF placement method for many previous technology nodes. Although RBAF algorithm
complexity limits its use with very extreme illumination, RBAF is still a powerful option in certain scenarios. One
example is for repeating patterns in memory arrays. RBAF algorithms can be finely optimized and verified
experimentally without the building of complex models. RBAF also guarantees AF placement consistency based only
on the very local geometric environment, which is important in applications where consistent signal propagation is of
MBAF algorithms deliver the ability to reliably place assist features for enhanced process window control across a wide
variety of layout feature configurations and aggressive illumination sources. These methods optimize sophisticated AF
placement to improve main feature PW but without performing full main feature OPC. The flexibility of MBAF allows
for efficient investigations of future technology nodes as the number of interactions between local layout features
increases beyond what RBAF algorithms can effectively support
Based on hybrid approach algorithms combining features of the different algorithms using both RBAF and MBAF
methods, the generation and placement of SRAF can be a good alternative. Combining of two kinds of SRAF placement
options might result in relatively improved process window compared to an independent approach since two methods
are capable of supplement each other with a complementary advantages.
In this paper we evaluate the impact of SRAF configuration to pattern profile as well as CD margin window and
manufacturing applications of MBAF and Hybrid approach algorithms compared to the current OPC without AF. As a
conclusion, we suggest methodology to set up optimum SRAF configuration using these AF methods with regard to
Model based optical proximity correction (MB-OPC) has been widely used in advanced lithography process today.
However controlling the edge placement error (EPE) and critical dimension (CD) has become harder as the k1 process
factor decreases and design complexity increases. Especially, for high-NA lithography using strong off-axis
illumination (OAI), ringing effects on 2D layout makes CD control difficult. In addition, mask rule check (MRC) limits
also prevent good OPC convergence where two segment edges are corrected towards each other to form a correction-conflicting
scenario because traditional OPC only consider the impact of the current edge when calculating the edge
movement. A more sophisticated OPC algorithm that considers the interaction between segments is necessary to find a
solution that is both MRC and convergence compliant.
This paper first analyzes the phenomenon of MRC-constrained OPC. Then two multiple segment correction techniques
for tolerance-based OPC and MRC-constrained OPC are discussed. These correction techniques can be applied to
selected areas with different lithographic specifications. The feasibility of these techniques is demonstrated by
quantifying the EPE convergence through iterations and by comparing the simulated contour results.
This paper presents a novel mask corner rounding (MCR) modeling approach based on Synopsys' Integrated Mask and
Optics (IMO) modeling framework. The point spread functions of single, double, and elliptical Gaussians are applied to
the IMO mask kernels to simulate MCR effects. The simulation results on two dimensional patterns indicate that the
aerial image intensity variation is proportional to the MCR induced effective area variations for single type corners. The
relationship may be reversed when multiple types of corners exist, where the corners close to the maximum intensity
region have a greater influence than others. The CD variations due to MCR can be estimated by the effective area
variation ratio and the image slope around the threshold. The good fitting results on line-end patterns indicate that the
ΔCD is the quadratic function of the Gaussian standard deviations. OPC modeling on 28nm-node contacts shows that
MCR has significant impact on model fitting results and process window controls. By considering the real mask
geometry effects and allowing in-line calibration of model parameters, the IMO simulation framework significantly
improves the OPC model accuracy, and maintains the calibration speed at a good level.
A precise lithographic model has always been a critical component for the technique of Optical Proximity Correction
(OPC) since it was introduced a decade ago . As semiconductor manufacturing moves to 32nm and 22nm technology
nodes with 193nm wafer immersion lithography, the demand for more accurate models is unprecedented to predict
complex imaging phenomena at high numerical aperture (NA) with aggressive illumination conditions necessary for
these nodes. An OPC model may comprise all the physical processing components from mask e-beam writing steps to
final CDSEM measurement of the feature dimensions. In order to provide a precise model, it is desired that every
component involved in the processing physics be accurately modeled using minimum metrology data. In the past years,
much attention has been paid to studying mask 3-D effects, mask writing limitations, laser spectrum profile, lens pupil
polarization/apodization, source shape characterization, stage vibration, and so on. However, relatively fewer studies
have been devoted to modeling of the development process of resist film though it is an essential processing step that
cannot be neglected. Instead, threshold models are commonly used to approximate resist development behavior. While
resist models capable of simulating development path are widely used in many commercial lithography simulators, the
lack of this component in current OPC modeling lies in the fact that direct adoption of those development models into
OPC modeling compromises its capability of full chip simulation. In this work, we have successfully incorporated a
photoresist development model into production OPC modeling software without sacrificing its full chip capability. The
resist film development behavior is simulated in the model to incorporate observed complex resist phenomena such as
surface inhibition, developer mass transport, HMDS poisoning, development contrast, etc. The necessary parameters are
calibrated using metrology data in the same way that current model calibration is done. The method is validated with a
rigorous lithography process simulation tool which is based on physical models to simulate and predict effects during the
resist PEB and development process. Furthermore, an experimental lithographic process was modeled using this new
methodology, showing significant improvement in modeling accuracy in compassion to a traditional model. Layout
correction test has shown that the new model form is equivalent to traditional model forms in terms of correction
convergence and speed.
At advanced technology nodes with extremely low k1 lithography, it is very hard to achieve image fidelity requirements and process window for some layout configurations. Quite often these layouts are within simple design rule constraints for a given technology node. It is important to have these layouts included during early RET flow development. Most of RET developments are based on shrunk layout from the previous technology node, which is possibly not good enough. A better methodology in creating test layout is required for optical proximity correction (OPC) recipe and assists feature development.
In this paper we demonstrate the application of programmable test layouts in RET development. Layout pattern libraries are developed and embedded in a layout tool (ICWB). Assessment gauges are generated together with patterns for quick correction accuracy assessment. Several groups of test pattern libraries have been developed based on learning from product patterns and a layout DOE approach. The interaction between layout patterns and OPC recipe has been studied.
Correction of a contact layer is quite challenge because of poor convergence and low process window. We developed test pattern library with many different contact configurations. Different OPC schemes are studied on these test layouts. The worst process window patterns are pinpointed for a given illumination condition.
Assist features (AF) are frequently placed according to pre-determined rules to improve lithography process window. These rules are usually derived from lithographic models and experiments. Direct validation of AF rules is required at development phase. We use the test layout approach to determine rules in order to eliminate AF printability problem.
Semiconductor manufacturers spend hundreds of millions of dollars and years of development time to create a new
manufacturing process and to design frontrunner products to work on the new process. A considerable percentage of this
large investment is aimed at producing the process design rules and related lithography technology to pattern the new
products successfully. Significant additional cost and time is needed in both process and design development if the
design rules or lithography strategy must be modified. Therefore, early and accurate prediction of both process design
rules and lithography options is necessary for minimizing cost and timing in semiconductor development.
This paper describes a methodology to determine the optimum design rules and lithography conditions with high
accuracy early in the development lifecycle. We present results from the 32nm logic node but the methodology can be
extended to the 22nm node or any other node. This work involves: automated generation of extended realistic logic test
layouts utilizing programmed teststructures for a variety of design rules; determining a range of optical illumination and
process conditions to test for each critical design layer; using these illumination conditions to create a extrapolatable
process window OPC model which is matched to rigorous TCAD lithography focus-exposure full chemically amplified
resist models; creating reticle enhancement technique (RET) recipes which are flexible enough to be used over a variety
of design rule and illumination conditions; OPC recipes which are flexible enough to be used over a variety of design
rule and illumination conditions; and OPC verification to find, categorize and report all patterning issues found in the
different design and illumination variations. In this work we describe in detail the individual steps in the methodology,
and provide results of its use for 32nm node design rule and process optimization.
As the semiconductor industry moves to the 45nm node and beyond, the tolerable
lithography process window significantly shrinks due to the combined use of high NA
and low k1 factor. This is exacerbated by the fact that the usable depth of focus at 45nm
node for critical layer is 200nm or less. Traditional Optical Proximity Correction (OPC)
only computes the optimal pattern layout to optimize its patterning at nominal process
condition (nominal defocus and nominal exposure dose) according to an OPC model
calibrated at this nominal condition, and this may put the post-OPC layout at nonnegligible
patterning risk due to the inevitable process variation (defocus and dose
variations). With a little sacrifice at the nominal condition, process variation aware OPC
can greatly enhance the robustness of post-OPC layout patterning in the presence of
defocus and dose variation. There is also an increasing demand for through process
window lithography verification for post-OPC circuit layout. The corner stone for
successful process variation aware OPC and lithography verification is an accurately
calibrated continuous process window model which is a continuous function of defocus
and dose. This calibrated model needs to be able to interpolate and extrapolate in the
usable process window. Based on Synopsys' OPC modeling software package ProGen,
we developed and implemented a novel methodology for continuous process window
(PW) model, which has two continuous adjustable process parameters: defocus and dose.
The calibration of this continuous PW model was performed in a single calibration
process using silicon measurement at nominal condition and off-focus-off-dose
conditions which are sparsely sampled within the measured entire focus exposure matrix
(FEM). The silicon data at the off-focus-off-dose conditions not used for model
calibration was utilized to validate the accuracy and stability of PW model during model
interpolation and extrapolation. We demonstrated this novel continuous PW modeling
approach can achieve very good performance both at nominal condition and at
interpolated or extrapolated off-focus-off-dose conditions.
At low k1 lithography and strong off-axis illumination, it is very hard to achieve edge-placement tolerances and 2-D
image fidelity requirements for some layout configurations. Quite often these layouts are within simple design rules
constraint for a given technology node. Evidently it is important to have these layouts included during early RET flow
development. Simple shrinkage from previous technology node is quite common, although often not enough. For logic
designs, it is hard to control design styles. Moreover for engineers in fabless design groups, it is difficult to assess the
manufacturability of their layouts because of the lack of understanding of the litho process.
Assist features (AF) are frequently placed according to pre-determined rules to improve lithography process window.
These rules are usually derived from lithographic models. Direct validation of AF rules is required at development
phase.To ensure good printability through process window, process aware optical proximity correction (OPC) recipes
were developed. Generally rules based correction is performed before model based correction. Furthermore, there are also
lots of other options and parameters in OPC recipes for an advanced technology, thus making it difficult to holistically
optimize performance of recipe bearing all these variables in mind.
In this paper we demonstrate the application of layout DOE in RET flow development. Layout pattern libraries are
generated using the Synopsys Test Pattern Generator (STPG), which is embedded in a layout tool (ICWB). Assessment
gauges are generated together with patterns for quick correction accuracy assessment. OPC verification through full
process is also deployed. Several groups of test pattern libraries for different applications are developed, ranging from
simple 1D pattern for process capability study and settings of process aware parameters to a full set of patterns for the
assessment of rules based correction, line end and corner interaction, active and poly interaction, and critical patterns for
contact coverage, etc.
Restrictive design rules (RDR) are commonly deployed to eliminate problematic layouts. We demonstrate RDR
evaluation and validation using our layout design of experiments (DOE) approach. This technique of layout DOE also
offers a simple and yet effective way to verify AF placement rules. For a given nominal layout features all possible assist
features are generated within the mask rules constraint using STPG. Then we run OPC correction and assess main feature
critical dimension (CD) at best and worst process condition in ICWB. Best assist feature placement rules are derived based
on minimum CD difference. The rules derived from this approach are not the same as those derived from the commonly
used method of least intensity variation.
In the past technology generations, Optical Proximity Correction (OPC) has been applied using a model
capturing the Optical proximity effects in a single focal plane. In the newer generations, this method is more and
more difficult to maintain because of very small process windows in specific situations. These specific situations
include 1D configurations (e.g. isolated small lines) but increasingly complex 2D configurations.
In the more advanced technology nodes 2D configuration are starting to play a much bigger role. Process
windows need to be preserved in all cases, and so this brings about another challenge for the OPC flow. The more
traditional OPC approaches may result in un-acceptable small process window in such cases, whereas well
characterized Process Window aware OPC (PW-OPC) can provide better results, with much less engineering
In this paper the method of Process Window aware OPC is applied on special designed test structures and on a
larger scale (full chip). Verifications and assessments are demonstrated and compared with alternatives. In the past
OPC engineers have been pushing for more and more design constraints in order to allow the OPC flow to be
successful. The PW-OPC approach is more adaptive compared with traditional single focal plane OPC, and can
still converge to an acceptable solution in complicated (unforeseen) layout configurations, without the need to
introduce complicated design constraints.
In the post-physical verification space called 'Mask Synthesis' a key component of design-for-manufacturing (DFM), double-exposure based, dark-field, alternating PSM (Alt-PSM) is being increasingly applied at the 90nm node in addition with other mature resolution enhancement techniques (RETs) such as optical proximity correction (OPC) and sub-resolution assist features (SRAF). Several high-performance IC manufacturers already use alt-PSM technology in 65nm production. At 90nm having strong control over the lithography process is a critical component in meeting targeted yield goals. However, implementing alt-PSM in production has been challenging due to several factors such as
phase conflict errors, mask manufacturing, and the increased production cost due to the need for two masks in the process. Implementation of Alt-PSM generally requires phase compliance rules and proper phase topology in the layout and this has been successful for the technology node with these rules implemented. However, this may not be true for a mature, production process technology, in this case 90 nm. Especially, in the foundry-fabless business model where the foundry provides a standard set of design rules to its customers for a given process technology, and where not all the foundry customers require Alt-PSM in their tapeout flow. With minimum design changes, design houses usually are motivated by higher product performance for the existing designs. What follows is an in-depth review of the motivation to apply alt-PSM on a production FPGA, the DFM challenges to each partner faced, its effect on the tapeout flow, and how design, manufacturing, and EDA teams worked together to resolve phase conflicts, tapeout the chip, and finally verify the silicon results in production.