The IBM Silicon Nanophotonics technology enables cost-efficient optical links that connect racks, modules, and chips together with ultralow power single-die optical transceivers. I will give an overview of its historical development, technology differentiators, current status and a roadmap.
Passive wavelength division (de)multiplexer (WDM) devices are required as basic building blocks for WDM-based on-chip
optical interconnects. In this application, many copies of the devices will be placed throughout a single die,
requiring that the device occupy as small a footprint as possible. Furthermore, it is critical that the demultiplexing
characteristics be very uniform from device to device, therefore the device must be tolerant to small fabrication
variations. There are various wavelength demultiplexer designs that lend themselves to on-chip integration with CMOS
integrated circuits and that could potentially reach the above specifications. In this presentation we will show the layout
and simulation of demultiplexer designs based on cascaded Mach-Zehnder wavelength splitters and on Echelle gratings
and compare these to measurement results of realized devices. The results on the Mach-Zehnder devices show that this
type of device is relatively sensitive to process variations. A fit of a device model to the measured curves shows that the
device variations result primarily from random phase errors in the optical delay lines, which are probably due to small
width variations in the waveguides. This problem should be strongly reduced in devices based on Echelle gratings,
because in this case the light does not propagate through channel waveguides in the part of the device that shapes the
optical response. This assumption is confirmed by the measurement results, which show good demultiplexer response
and excellent reproducibility between devices.
Scaling computing systems to Exaflops (1018 floating point operations per second) will require tremendous increases in
communications bandwidth but with greatly reduced power consumption per communicated bit as compared to today's
petaflop machines. Reaching the required performance in both density and power consumption will be extremely
challenging. Electrical and optical interconnect technologies that may be part of the solution are summarized, including
advanced electrical printed circuit boards, VCSEL-array based optical interconnects over multimode fibers or
waveguides, and singlemode silicon photonics. The use of optical interconnects will play an ever-larger role in
intrasystem communications. Although optics is used today primarily between racks, it will gradually migrate into
backplanes, circuit cards, and eventually even on-chip.
Keywords: optical interconnects, supercomputers, exascale,
We present ultra-compact integrated optical echelle grating WDM (de-)multiplexers for on-chip optical networks. These
devices are based on a design with two stigmatic points. The devices were fabricated using Silicon-On-Insulator (SOI)
photonic waveguide technology thus the smallest version of the (de-)multiplexer occupies an area of only 250x200 μm.
We will show measurement results on different variations of the echelle grating devices. In the measurements, we found
a channel to channel isolation of 19 dB. The minimum insertion loss, relative to a straight waveguide, is only 3 dB with a
channel to channel variation of 0.5 dB.nefit of the numerical reconstruction properties of DH in combination with
diffraction grating to get super-resolution. Various attempts have been performed and results are presented and
discussed. The approaches could be used for metrology and imaging application in various fields of engineering and biology.
The continued scaling of power performance in electronic hardware for high-performance computing is rapidly being
limited due to the large power consumption and restricted throughput of traditional electrical interconnects. One possible
solution is to replace conventional global interconnects with a CMOS compatible intra-chip optical network, based on
Silicon-On-Insulator (SOI) photonic integrated circuits. While the bandwidth and power consumption advantages of SOI
optical interconnects are potentially immense, ensuring the performance of chip-scale networks places stringent
requirements upon the control of the manufacturing process, and its influence upon the operation of individual optical
components. I will present recent work on the design, fabrication, and demonstration of various passive and electrooptic
devices required for high speed optical interconnect applications, including high-order optical filters and modulators.
Various aspects of the CMOS compatible fabrication process used at IBM Research for manufacturing SOI photonic
wire circuits will be discussed, including waveguide loss, surface roughness, device dimensions, and microresonator
We employ ultranarrow silicon-on-insulator (SOI) waveguides to demonstrate significant Raman gain using low CW pump powers from a diode laser. Starting with measurements based on spontaneous Raman scattering in nanowire SOI waveguides, we obtain the parameters necessary to develop a useful numerical modeling tool for our system. This work shows clearly the feasibility of an SOI-based low-loss, low-power, on-chip Raman amplifier in the silicon nanowire system. We have also developed a rigorous coupled wave model to examine temporal effects in our Raman system.
We investigate both experimentally and theoretically the waveguiding
properties of the novel design of channel waveguides in
silicon-on-insulator (SOI) photonic crystal slabs. It is known that
the channel waveguides defined by a missing of one row of holes in a
triangular-lattice photonic crystal are characterized by a very narrow transmission bandwidth limited by large group velocity dispersion. In order to increase the bandwidth we investigate an alternative design, where the conventional single-mode strip waveguide is embedded into a photonic crystal slab -- a so-called double-trench waveguide. Such a design is intended to combine the best features of photonic crystal slabs, such as suppression of radiation losses at bends and imperfections, with broad bandwidth and small group velocity dispersion. We report the successful demonstration of this broad-bandwidth photonic crystal waveguide with propagation losses as low as 35 dB/cm, which are among the lowest reported in the literature. Furthermore, we found that the modes of positive (quasi-TE) and negative (quasi-TM) parity significantly interact in our structures due to the absence of the oxide layer on top of the SOI slab and the resulting asymmetry. As a result of this interaction multiple mini-stopbands appear in the areas of anti-crossing of the positive and negative parity modes. The results are successfully modeled by the plane-wave calculations confirming the nature of the experimentally observed mini-stopbands. To the best of our knowledge this is the first demonstration of the effects of asymmetry on the transmission characteristics of the photonic crystal slabs.
The application of sensitive layers for chemical microsensors consisting of multicomponent compositions and dielectric materials requires specific deposition techniques, since the different chemical and physical properties of the respective components can be significantly disturbed during the deposition process. To avoid this drawback, the pulsed laser deposition technique is suggested as a novel thin film preparation method for such sensor devices.