We have fabricated seven masks with different patterns on a 27 mm x 34 mm single-membrane for Low Energy Electron-beam Proximity Lithography (LEEPL) by the wafer-flow process. We have examined the membrane flatness and image placement (IP) accuracy, which are essential qualities to be assured. We summarize the results as follows: Masks with membranes of 13 MP and 20MPa stress satisfy the membrane flatness requirement of less than 2 μm while a mask with a 6 MPa membrane does not. Maps of the distortion induced by the wafer-flow process are obtained for the masks with 13 MPa and 20 MPa membranes and their performance is explained in terms of the contraction of the mask substrate. The out-of-plane distortion for a 3 mm x 3 mm block of dense hole patterns with an opening ratio, ranging from 10% to 40%, has been evaluated. The distortion induced by the block has been evaluated and the effect of the local magnification correction on the IP error is examined. Maps of the distortion induced by the wafer-flow process and 4 x 4 blocks of 10% and 20% opening are obtained for a mask with 13 MPa membrane and the distortion induced by the blocks is estimated in 3σ. The uncorrectable IP error for the mask with the blocks of 10% opening is estimated to be 10 nm (in 3σ), which satisfies the specification for LEEPL masks.
Masks for low energy electron proximity projection lithography (LEEPL) are fabricated starting with 200 mm silicon-on-insulator (SOI) wafers. The effect of the thickness of the buried oxide (BOX) layer of an SOI wafer on its flatness has been investigated. The wafer flatness is found to decrease as the BOX layer becomes thin. When the SOI layer (Si membrane) is not doped by B or P, the membrane has a compressive stress even for a 0.2 μm thick BOX layer. A monitor mask with image placement (IP) marks on a single-large (24 mm square) membrane area has been fabricated, starting with an SOI wafer with an 1.1 μm thick stress-controlled SOI layer and a 0.2 μm thick BOX layer. The internal stress of the membrane was 19 +/- 6 MPa (3σ) (tensile), and the membrane flatness was 0.8 μm. An ES chuck for an LSM-IPRO, which holds a mask in the method compatible with that in LEEPL exposure tools, has been installed. Chucking reduced the mask flatness from 22 μm to 10 μm while the membrane flatness was kept less than 1.0 µm. The dynamic repeatability of IP measurement was 7.6 nm (x) and 4.8 nm (y) in 3σ. The IP error of the monitor mask that had only IP marks was 17 nm (x) and 17 nm (y) in 3σ, satisfying the specification of 30 nm or less.
200-mm electron-beam projection lithography (EPL) masks were fabricated starting from stress-controlled silicon-on-insulator (SOI) substrates. The internal stress of the SOI layer is controlled to be ca. 10 MPa by B doping. The blank fabrication process has been established by the Bosch deep trench etch process. EB patterning was done on a JEOL JBX9000MVII with a positive-tone chemically amplified resist of 400-nm thickness. Resist image of 200-nm wide lines-and-spaces pattern was transferred to 2-um thick SOI layer by a shallow trench etching. A dual-mode critical dimension (CD)-SEM was implemented, and used for mask characterization. Preliminary results on uniformity of CD-shift in the dry etching and final CD were reported. 200-mm EPL masks with a gate layer of a system-on-chip device pattern were fabricated.
Low energy electron proximity projection lithography (LEEPL) has three types of mask formats. One of them, LEEPL 6025 square format, is so designed that electron-beam writers for photomasks can accommodate it. LEEPL 6025 square format blanks manufactured by three methods were evaluated in laying stress on cutting and bonding. The starting substrate was a 200-mm silicon-on-insulator wafer composed of a 2-μm-thick silicon layer, a 1-μm-thick SiO<sub>2</sub> layer, and a 725-μm-thick base silicon. Membrane wafers were made after dry etching of the backsides of the starting substrates. They were cut and bonded to frames. Ceramic SiC and a Si-base material were used for the frame. Soldering and other thermal methods were employed for bonding. The findings are: 1) No membranes were broken in cutting and bonding, 2) Chipping was observed after cutting, which requires some edge treatment like edge beveling, and 3) The flatness of the membrane wafer was reduced from 87 to 13 μm by bonding. In conclusion the 6025 square format blanks were successfully manufactured by three methods and evaluated in the first time.
In EPL, one of the issues is how to reduce the critical dimension (CD) error observed at the boundary of two complementary patterns when being stitched together to form one smooth line. This paper is concerned about edge deformation of the two lines to reduce the CD error. Among several forms, a pair of concave- and convex-three-up-step edges was formed for 580-nm-wide lines with 75-nm-wide steps. Our choices of the shapes of deformed edges are presented based on the degree of difficulties of making fiber features on mask. The first choice is a pair of concave- and convex-one-step edges. Two EPL dat conversion systems, SX-GIGA/EPLON of Seiko Instruments Inc. and PATACON-6600 of Nippon Control System Corp., are introduced. They are found to automatically yield required stitching correction patterns. Their flexibility in stitching correction enough to cope with customers' requests makes them useful and practical.