Self-Aligned Via (SAV) process is commonly used in back end of line (BEOL) patterning. As the technology node advances, tightening CD and overlay specs require continuous improvement in model accuracy of the SAV process. Traditional single layer Variable Etch Bias (VEB) model is capable of describing the micro-loading and aperture effects associated with the reactive ion etch (RIE), but it does not include effects from under layers. For the SAV etch, a multi-layer VEB model is needed to account for the etch restriction from metal trenches. In this study, we characterize via post-etch dimensions through pitch and through metal trench widths, and show that VEB model prediction accuracy for SAV CDs after SAV formation can be significantly improved by applying a multi-layer scheme. Using a multi-layer VEB, it is demonstrated that the output via size changes with varying trench dimensions, which matches the silicon results. The model also reports via shape post-etch as a function of trench environment, where elliptical vias are correctly produced. The multi-layer VEB model can be applied both multi-layer correction and verification in full chip flow. This paper will also suggest that the multi-layer VEB model can be used in other FEOL layers with interlayer etch process effects, such as gate cut, to support the robustness of new model.
In advanced DRAM manufacturing, the process scaling to increase memory cell density creates a difficult challenge for
conventional optical or SEM metrology tools to characterize wafer surface profiles after plasma etching. Dry plasma
etch processes are used to form critical contact plugs within a stacked capacitor DRAM cell, two of which will be
discussed in this article. One contact plug connects a buried digit line to an active area in array, while another contact
plug connects a capacitor container to an active area through the first plug. In both cases, the etched surface structure
features a complex three-dimensional (3D) topography with a minimum space at ~50nm (see Figure 1). Etch profiles are
directly related to the DRAM yield and must be monitored inline. Scanning probe based atomic force microscopy
(AFM) is particularly beneficial for this type of dimension measurements. This article presents the methodology and
recent results of applying AFM as inline metrology for contact etch control at 70nm node and below. AFM is an
advanced, high-resolution 3D imaging tool. It provides nondestructive and direct in-die measurements of the active
circuit region on product wafers at the contact etch steps and other critical process layers. Calculated automatically from
AFM images, the dry etch depth is used as inline metrology for process control and is a critical metric for process
Proc. SPIE. 3882, Process, Equipment, and Materials Control in Integrated Circuit Manufacturing V
KEYWORDS: Oxides, Polishing, Metrology, Detection and tracking algorithms, Reflectivity, Control systems, Process control, Algorithm development, Semiconducting wafers, Chemical mechanical planarization
Oxide chemical mechanical polishing process control has been limited in the past to off-line verification of layer thicknesses. This procedure causes a significant delay in feedback due to the off-line scrubbing process and wafer transfer. Recently, systems have been introduced to endpoint on the polish platen itself using interference-based methods. While these approaches allow a better control of the thickness remaining, they do not replace the off-line measurement because the correlation of the signal with the absolute thickness is difficult and no uniformity information is retrieved. An integrated measurement tool, that provides feedback immediately after the polish cycle, represents an intermediate solution. This methodology reduces the set-up time significantly and allows a 100% control of the outgoing product with increased throughput versus using an off-line measurement system. In respect to optimizing the wafer to wafer variation within lot, the polish time can be adjusted for the subsequent wafer based on the previously polished wafers. The utilized closed loop control algorithm (PID-type) can take the incoming distribution into account as well as first wafers effects and changes in layer type. Considering the results of the measurement of previously polished wafers, the polish time for the following wafer is adjusted to center the thickness distribution around the target. A system as described was implemented on an IPEC 472 polisher at Motorola MOS6. Lot charts showing thickness variations before and after the implementation of CLC have been recorded showing an improved distribution with CLC feedback leading to improvements in process capability by a factor of 1.5. In summary, integrated metrology with closed loop control provides improved process control as well as enhanced throughput for oxide CMP.