Due to photolithography effects and manufacture process variations, the actual features printed on wafer are different from the designed ones. This difference results in the inaccuracy on parasitic extraction, which is critical for timing verification and design for manufacturability. Most of the current layout parasitic extraction (LPE) tools ignore these effects and can cause as high as 20% errors. This paper proposes a new strategy to extract interconnect parasitics with the consideration of photolithography effects and process variations. Based on the feedback from lithography simulation, a shape correction process is setup to adjust the interconnect structure for LPE tools. Compared with the traditional extraction methodology, the parasitics extracted from this adjusted geometry are more accurate. This method can be implanted into the current design flow with minimum change. Meanwhile, this paper studies the impacts of mask critical dimension (CD) variations on interconnect parasitics. The variability analysis is based on PROLITH lithography simulation software and is tested on RAPHAEL interconnect library. The results show a high nonlinear relationship between the mask variation and the interconnect parasitics.