Mr. Yves T. LaPlanche Profile

Yves T. LaPlanche

at STMicroelectronics

SPIE Involvement:

Author

Publications (5)

PROCEEDINGS ARTICLE | May 20, 2004

Manufacturing concerns for advanced CMOS circuit realization EBDW alternative solution for cost and cycle time reductions

Proc. SPIE. 5374, Emerging Lithographic Technologies VIII

KEYWORDS: Lithography, Electron beam lithography, Manufacturing, Control systems, Photomasks, Optical alignment, Electron beam direct write lithography, Photoresist processing, Semiconducting wafers, Optics manufacturing

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PROCEEDINGS ARTICLE | June 16, 2003

Advanced patterning studies using shaped e-beam lithography for 65-nm CMOS preproduction

Proc. SPIE. 5037, Emerging Lithographic Technologies VII

KEYWORDS: Oxides, Lithography, Electron beam lithography, Etching, Scanners, Chemistry, Photomasks, CMOS technology, Optical alignment, Semiconducting wafers

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PROCEEDINGS ARTICLE | June 16, 2003

Mix and match capability of e-beam direct-write for the 65-nm technology

Proc. SPIE. 5037, Emerging Lithographic Technologies VII

KEYWORDS: Electron beam lithography, Optical lithography, Scanners, Error analysis, Distortion, Photomasks, Optical alignment, Electron beam direct write lithography, Semiconducting wafers, Overlay metrology

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PROCEEDINGS ARTICLE | July 24, 2002

Negative-tone CAR resists for e-beam lithography: modification of chemical composition for R&D application (high resolution) or production application (high sensitivity)

Proc. SPIE. 4690, Advances in Resist Technology and Processing XIX

KEYWORDS: Lithography, Electron beam lithography, Etching, Polymers, Diffusion, Palladium, Critical dimension metrology, Semiconducting wafers, Prototyping, Industrial chemicals

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PROCEEDINGS ARTICLE | July 1, 2002

Shaped e-beam lithography integration work for advanced ASIC manufacturing: progress report

Proc. SPIE. 4688, Emerging Lithographic Technologies VI

KEYWORDS: Lithography, Electron beam lithography, Optical lithography, Etching, Manufacturing, Photomasks, Photoresist processing, Semiconducting wafers, Prototyping, Standards development

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