In this work a novel machine learning algorithm is used to calculate the after etch overlay of the memory holes in a 3DNAND device based on OCD metrology by YieldStar S1375. It is shown that the method can distinguish the overlay signals from the process induced signals in the acquired pupil image and therefore, enables for an overlay metrology approach which is highly robust to process variations. This metrology data is used to characterize and correct the process induced intra-die stress and the DUV scanner application fingerprint.
This paper demonstrates the improvement using the YieldStar S-1250D small spot, high-NA, after-etch overlay in-device measurements in a DRAM HVM environment. It will be demonstrated that In-device metrology (IDM) captures after-etch device fingerprints more accurately compared to the industry-standard CDSEM. Also, IDM measurements (acquiring both CD and overlay) can be executed significantly faster increasing the wafer sampling density that is possible within a realistic metrology budget. The improvements to both speed and accuracy open the possibility of extended modeling and correction capabilities for control. The proof-book data of this paper shows a 36% improvement of device overlay after switching to control in a DRAM HVM environment using indevice metrology.
The high-NA angle-resolved scatterometer YieldStar 1250D, with a small 12x12μm2 inspection area, has been used to inspect CD variation After Develop (ADI) and After Partition/Final Etch (APEI/AFEI) on various layers and features of a HVM DRAM process. During recipe set-up, CD-SEM data were used to verify full recipe quality. The high sampling density enabled by the small inspection area and high speed of the YieldStar angle-resolved scatterometer could be used to reveal various kinds of CD variations. An intra-field control-loop with scanner dose corrections was tested, using very dense ADI and APEI measurements, 400ppf, 4fields. This strategy demonstrated a 21% improvement in intra-field CDU, in line with expectations from predictions. Inter-field control loops with different strategies have been simulated for APEI CD control. To capture all variations in the inter-field fingerprints a dense sampling, 24ppf full wafer, in combination with a dynamic, context-based control strategy, appeared to be necessary. An improvement of 30% of the wafer CDU (excluding the intra-field) is feasible. For the Self-Aligned Double Patterning process, essential for the dense DRAM cells, the CD variation at APEI contributes to pitch-walking at final etch. Pitch walking is an alternating OV error, therefore these control strategies will also contribute to improvement of the OV control budget.
Spacer multi patterning process continues to be a key enabler of future design shrinks in DRAM and NAND process flows. Improving Critical Dimension Uniformity (CDU) for main features remains high priority for multi patterning technology and requires improved metrology and control solutions.
In this paper Spacer Patterning Technology is evaluated using an angle resolved scatterometry tool for both intra field control of the core CD after partition etch (S1) and interfield pitch-walking control after final etch (S1-S2). The intrafield measurements were done directly on device using dense sampling. The inter-field corrections were based on sparse full wafer measurements on biased OCD targets. The CDU improvement after partition-etch was verified by direct scatterometer and CD-SEM measurement on device. The final etch performance across wafer was verified with scatterometer on OCD target.
The scatterometer metrology in combination with the control strategy demonstrated a consistent CDU improvement of core (S1) intrafield CD after partition etch between 23-39% and 47-53% on interfield pitch-walking (S1-S2) after final etch. To confirm these improvements with CD-SEM, oversampling of more than 16 times is needed compared to scatterometer.
Based on the results it is concluded that scatterometry in combination with the evaluated metrology and control strategy in principle qualifies for a spacer process CDU control loop in a manufacturing environment.