Proc. SPIE. 9675, AOPC 2015: Image Processing and Analysis
KEYWORDS: Point spread functions, Digital signal processing, Image processing, Image restoration, Computing systems, Field programmable gate arrays, Parallel processing, Data processing, Deconvolution, Image deconvolution
Image restoration takes a crucial place in several important application domains. With the increasing of computation requirement as the algorithms become much more complexity, there has been a significant rise in the need for accelerating implementation. In this paper, we focus on an efficient real-time image processing system for blind iterative deconvolution method by means of the Richardson-Lucy (R-L) algorithm. We study the characteristics of algorithm, and an image restoration processing system based on the coordinated framework of FPGA and DSP (CoFD) is presented. Single precision floating-point processing units with small-scale cascade and special FFT/IFFT processing modules are adopted to guarantee the accuracy of the processing. Finally, Comparing experiments are done. The system could process a blurred image of 128×128 pixels within 32 milliseconds, and is up to three or four times faster than the traditional multi-DSPs systems.
Proc. SPIE. 8005, MIPPR 2011: Parallel Processing of Images and Optimization and Medical Imaging Processing
KEYWORDS: Point spread functions, Digital signal processing, Detection and tracking algorithms, Image processing, Image restoration, Field programmable gate arrays, Parallel processing, Data processing, Signal processing, Deconvolution
In this paper, we present a co-design method for parallel image processing accelerator based on DSP and FPGA. DSP is
used as application and operation subsystem to execute the complex operations, and in which the algorithms are
resolving into commands. FPGA is used as co-processing subsystem for regular data-parallel processing, and operation
commands and image data are transmitted to FPGA for processing acceleration. A series of experiments have been
carried out, and up to a half or three quarter time is saved which supports that the proposed accelerator will consume less
time and get better performance than the traditional systems.