FinFETs have demonstrated significant performance improvement compared to planar devices, because of its superior short channel control and higher driving capability at a much smaller footprint. It has become the mainstream technology in CMOS industry since N20 node onward. Contact Poly Pitch (CPP) scaling used to be the main driving force in extending Moore’s law. However, severe limitations are foreseen from N3 node in terms of electrical performance, process requirements and manufacturing complexity. At N3 node, both fin and gate pitches are expected to reach their ultimate values, respectively 21 nm and 42 nm. Therefore, complex plasma etching processes using advanced plasma pulsing modes or atomic layer etching (ALE) are deployed to achieve high aspect ratio patterning capability with a detrimental effect on both process control and throughput. As an alternative, device architecture innovation will become the main scaling driving force for N3 node and beyond. 2D scaling like horizontal Gate-All-Around (GAA) devices, such as nanosheet (NS) and forksheet (FS) have demonstrated the potential for further device performance improvement [1,2]. The major NS patterning challenges are the SiGe lateral etch in the Si/SiGe superlattice stack and severe depth micro-loading due to the etch rate difference of SiGe and Si. In addition, 3D hybrid device architectures like Complementary FET (CFET) and Surrounding-Gate-Transistors (SGT) are proposed as revolutionary innovations to scale the devices in the vertical direction. For CFET devices, the N/P separation is moved to the vertical direction by stacking nMOS on top of pMOS or vice versa to achieve aggressive device scaling. This requires extremely high aspect ratio fin and gate patterning compared to horizontal-GAA NS devices. For SGT device, the channel is switched to the vertical direction, which can decouple the Gate length (Lg) from CPP scaling and eliminate the diffusion break to deeply scale the cell size. High aspect ratio vertical nanowire (NW) and direct metal gate etching with tight pitch are the new FEOL patterning challenges for the fabrication of SGT vertical devices.
In this paper proof-of-principle demonstrations of spin-on carbon (SOC)/spin-on glass (SOG)-based lithography processes which could replace standard patterning stacks within the FEOL for upcoming advanced nodes like N10/N7 are presented. At these dimensions the standard lithography approaches that have been utilized within the previous nodes will begin to run into fundamental limitations as a result of the extremely high aspect ratios of the device topography, requiring both new materials as well as new patterning flows in order to allow for continued device scaling. Here, novel SOC/SOG-based patterning flows have been demonstrated which could be applied to implement Source Drain Extension implantations and epitaxial growth processes for CMOS FinFET device architectures even down at N10/N7 dimensions.
Conventional photoresist processing involves resist coating, exposure, post-exposure bake, development, rinse and spin drying of a wafer. DDRP mitigates pattern collapse by applying a special polymer material (DDRM) which replaces the exposed/developed part of the photoresist material before wafer is spin dried. As noted above, the main mechanism of pattern collapse is the capillary forces governed by surface tension of rinse water and its asymmetrical recession from both sides of the lines during the drying step of the develop process. DDRP essentially eliminates these failure mechanisms by replacing remaining rinse water with DDRM and providing a structural framework that support resist lines from both sides during spin dry process. Dry development rinse process (DDRP) eliminates the root causes responsible for pattern collapse of photoresist line structures. Since these collapse mechanisms are mitigated, without the need for changes in the photoresist itself, achievable resolution of the state-of-the-art EUV photoresists can further be improved.
Si FinFET scaling is getting more difficult due to extremely narrow fin width control and power dissipation. Nanowire FETs and high mobility channel are attractive options for CMOS scaling. Nanowire FETs can maintain good electrostatics with relaxed nanowire diameter. High mobility channel can provide good performance at low power operation. However their fin patterning is challenging due to fins consisted of different materials or fragile high mobility material. Controlled etch and strip are necessary for good fin cd and profile control. Fin height increase is a general trend of scaled FinFETs and nanowire FETs, which makes patterning difficult not only in fin, but also in gate, spacer and replacement metal gate. It is important that gate and spacer etch have high selectivity to fins and good cd and profile control even with high aspect ratio of fin and gate. Work function metal gate patterning in scaled replacement metal gate module needs controlled isotropic etch without damaging gate dielectric. SF6 based etch provides sharp N-P boundary and improved gate reliability.
Pattern collapse currently limits the achievable resolution of the highest resolving EUV photoresists available. The causes of pattern collapse include the surface tension of the rinse liquid and the shrinkage of the resist pattern during the drying step. If these collapse mechanisms can be successfully mitigated with process approaches that do not require changes to the resist itself, the ultimate resolution of existing EUV resists can be improved. Described here is a dry development rinse process, applicable to existing EUV photoresists, which prevents pattern collapse to both improve ultimate resolution and the process window of currently resolvable features. Reducing the burden of collapse prevention on the resist also allows improvements in line width roughness (LWR) and cross section profile and provides additional degrees of freedom for future resist design.
In this paper, we will present the experimental comparison results on contact holes (CHs) and pillars patterning in EUV lithography with several candidate processes. Firstly, we have compared the normalized image log-slope (NILS), local critical dimension uniformity (LCDU) and dose-to-size (DtS) with respect to positive tone imaging (PTI) and negative tone imaging (NTI) process by EUV stochastic simulation. From the simulation results, we found that NTI process has higher absorbed photon density that can reduce the DtS and the LCDU of pillars pattern is improved with higher NILS compared to CHs patterning with similar DtS. So we have experimentally evaluated the pillars patterning process with 0.25NA EUV scanner system and compared the process margin, LCDU and DtS with the same parameters of the CHs pattering process. Further, we have demonstrated the CHs patterning with reverse process from pillars by using the dry development rinse process (DDRP). Different to the simulation results, the experimental LCDU results of pillars pattern and CHs pattern by DDRP show worse values comparing with the reference resist CHs pattern. In order to analyze these results, we have investigated the effect of flare, target CD, PR thickness and mask stack of the experimental conditions. Furthermore, we have evaluated the pillar patterning with NTD resist and by DDRP.
An inverse problem of ocean optics is solved for estimating the scalar irradiance and a source, such as fluorescence, bioluminescence, or Raman scattering, or an optical property such as the absorption coefficient. The solution requires in situ measurements of the downward and upward irradiances and a priori estimation of the angular shape of the volume scattering function. The iterative inversion procedure is developed from asymptotic two-stream radiative transfer equations and the conjugate gradient method. Preliminary numerical tests show that the algorithm is quite accurate in the region away from the surface but gives appreciable errors close to the surface where the asymptotic two-stream equations are a poor approximation.
Preliminary results are reported for estimating the spatial profile of bioluminescence in seawater from in situ measurements of the downward and upward irradiance and scalar irradiance. The explicit estimation method is based on the two stream approximation to radiative transfer and enables an estimation of the bioluminescence with two fitted parameters that require a previous estimation of the angular shape of the volume scattering function. The implicit estimation method is an iterative approach that utilizes the conjugate gradient method. Both methods enable one to estimate the bioluminescence when the absorption coefficient is not known. A comparison of numerical results from the two methods is given.