This paper presents a multiphase clock generation circuit (MPCG) using delay locked loop (DLL). In order to
achieve process independence, fixed bandwidth to operating frequency ratio, broad tuning range, and low jitter, the DLL
design is based on self-biased technique augmented with jitter attenuation technique, which can achieve precise delay
equal to the input reference clock period. Simulated in 65nm CMOS technology, the MPCG achieves an operating
frequency range of 1.8GHz to 4GHz. And the MPCG will generate eight clocks evenly spaced by 45 degrees. At
2.5GHz, its peak to peak jitter with quiescent supply is 10ps, and its power consumption is 11mW.