It Researches key technologies and hardware node structure of the Transport MPLS packet network. Main technology is
super high speed FPGA. The transport plane adapts the layer 3 service signals from client equipments and forwards them.
There are two types of node in transport plane, edge node (EN) or core node (CN), and the nodes realized with large-scale
FPGA chip have three main function units and six types of board. The EN adapts the layer 3 service signals such as
TDM, Packet and Cell to TM signals by add shim. The CN is responsible for the TM signals switching in higher speed
than traditional packet network such as Ethernet. Control plane is embedded in a FPGA chip and designed based on the
ASON core technique (GMPLS) such as the transport label switching path (T-LSP) maintaining (set up, release, state
monitoring), route controlling and protect recovering and so on.
Discusses the network architecture designed for providing carrier class metro Ethernet services over T-MPLS packet
transport network. Analyzes its characteristics and advantages from the aspects of data transport, OAM, end-to-end QoS,
protection mechanism and interworking.
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