With ever increasing requirements posed by significant advances in networking, service providers may use traffic
engineering (TE) techniques to efficiently manage resources and provide consistent quality of service (QoS). Briefly,
constraint-based path computation involves the pruning of links that do not satisfy constraints and subsequently using the
shortest path algorithm on the resulting sub-graph. This process is simple and efficient when the path involves only one
domain, but can potentially become severely resource heavy, complex, and inefficient when multiple domains are
involved. To address this problem, the Path Computation Element (PCE) architecture has been proposed to allow multilayer
path computation to be simple and efficient. The PCE architecture introduces a special computational entity that
will cooperate with similar entities to compute the best possible path through multiple layers. This paper analyses the
PCE architecture and the traditional method to computing the routing through multiple layers, and then an improved
scheme of path selection for multi-layer network based on PCE and VNTM is present and evaluated on the simulation
platform of NSFNET, which is used to avoid traffic redundancy caused by low layer's invisibility to the high layer.
Although Gigabit T-MPLS technology has not been widely used for transmission network, it is attracting more and more
attention. The design of high-speed data switching is the key technology in T-MPLS. In this paper, one method that
implements 4 ports Gigabit T-MPLS switch chip on FPGA which is used for TDM over T-MPLS exchanging is
introduced, and the simulation and verification results will be given in the conclusions. It researches the requirements of
transport plane in T-MPLS and analyses the architecture, and demonstrates a design of TDM in Transport MPLS based
on FPGA through a testbed which is used to explore and implement the concepts of Transport MPLS.
It Researches key technologies and hardware node structure of the Transport MPLS packet network. Main technology is
super high speed FPGA. The transport plane adapts the layer 3 service signals from client equipments and forwards them.
There are two types of node in transport plane, edge node (EN) or core node (CN), and the nodes realized with large-scale
FPGA chip have three main function units and six types of board. The EN adapts the layer 3 service signals such as
TDM, Packet and Cell to TM signals by add shim. The CN is responsible for the TM signals switching in higher speed
than traditional packet network such as Ethernet. Control plane is embedded in a FPGA chip and designed based on the
ASON core technique (GMPLS) such as the transport label switching path (T-LSP) maintaining (set up, release, state
monitoring), route controlling and protect recovering and so on.