A high-performance switched optical interconnection network is designed. The top layer of optical fiber ring network builds upon wavelength division multiplexing and hardware routing technologies. The bottom layer of star network has a throughput of 10 Gbit/s based on an 8-channel digital cross-point switch. Two types of optical network interface cards are developed to meet the requirements of interconnection bandwidth and support PCI bus full bandwidth of 1.056 Gbit/s and 4.224 Gbit/s, respectively. Field programmable gate array (FPGA) is adopted for frame head analysis, hardware routing and dynamic switch configuration. By adding a subnet to enlarge the network, the maximal delay increment is only 1.5 μs.
An 8-channel switching node with routing function is designed in this paper using a high-performance digital cross-point switch. The throughput of the 8-channel routing node is 10 Gbit/s. Combined with time division multiplexing (TDM) technique, a high-speed optical interconnection network was designed. Using Optical Network Interface Cards (ONIC) and the designed routing node, a two-layer optical interconnection network with structure of ring and star topology is designed. Based on circuits cascading technique, the network can be expanded to meet the request of large scale data communication with low communication latency.
Both hardware and software are optimized simultaneously to improve the bus throughput of node computer in cluster computing network. A cost effective optical interconnection ring network is established using off-the-shelf PCs with windows operating system. A network adapter card ONIC is developed. Using ETDM and field program technique, the full bandwidth of the 32bit×33MHz PCI bus is reached in physical layer. In order to overcome the hardware and software data bottlenecks induced by using of general purpose platform such as PCs and Windows 2000 system, several methods are adopted to maximum the bus throughput of node computer. A user-level interface is designed to blur the kernel/user mode boundary of the software system, and bypass the OS overhead. Zero-copy DMA is realized. The bandwidth in application level using PIO and DMA transfer mode is improved 17 and 26 times respectively. The sustained bandwidth in application layer can reach 437.6Mbit/s. It’s also shown theoretically and experimentally that the selection of main board chipset, using memory space map, reasonable using of PIO and DMA transfer mode, using polling and large MTU will also improve the bus throughput of node computer considerably.