As we advances into 14/10nm technology node, single patterning technology is far from enough to fabricate the
features with shrinking feature size. According to International Technology Roadmap for Semiconductors in
2011,1 double patterning lithography is already available for massive productions in industry for sub-32nm half
pitch technology node. For 14/10nm technology node, double patterning begins to show its limitations as it uses
too many stitches to resolve the native coloring conflicts. Stitches will increase the manufacturing cost, lead
to potential functional errors of the chip, and cause the yield lost. Triple patterning lithography and E-Beam
lithography are two emerging techniques to beat the diffraction limit for current optical lithography system. In
this paper, we investigate combining the merits of triple patterning lithography and E-Beam lithography for
standard cell based designs. We devise an approach to compute a stitch free decomposition with the optimal
number of E-Beam shots for row structure layout. The approach is expected to highlight the necessity and
advantages of using hybrid lithography for advanced technology node.
At the 7 nm technology node, the contact layers of integrated circuits (IC) are too dense to be printed by single exposure lithography. Block copolymer directed self-assembly (DSA) has shown its advantage in contact/via patterning with high throughput and low cost. To pattern contacts with DSA, guiding templates are usually printed first with conventional lithography, e.g., 193 nm immersion lithography (193i) that has a coarser pitch resolution. Contact holes are then patterned with DSA process. The guiding templates play the role of controlling the DSA patterns inside, which have a finer resolution than the templates. The DSA contact pitch depends on the chemical property of block copolymer and it can be adjusted within a certain range under strong lateral confinement to deviate from the natural pitch. As a result, different patterns can be obtained through different parameters. Although the guiding template shapes can be arbitrary, the overlay accuracy of the contact holes patterned are different and largely depend on the templates. Thus, the guiding templates that have tolerable variations are considered as feasible, and those have large overlays are considered as infeasible. To pattern the contact layer in a layout with DSA technology, we must ensure that all the DSA templates in the layout are feasible. However, the original layout may not be designed in a DSA-friendly way. Moreover, the routing process may introduce contacts that can only be patterned by infeasible templates. In this paper, we propose an optimization algorithm that optimize the contact layer for DSA patterning in 1D standard cell design. In particular, the algorithm modifies the layout via wire permutation technique to redistribute the contacts such that the use of infeasible templates is avoided and the feasible patterns that with better overlay control are favored. The experimental result demonstrate the ability of the proposed algorithm in helping to reduce the design and manufacturing cost of a DSA-enabled process at 7 nm technology node.
In detailed routing for integrated circuit (IC) designs, vias are usually randomly inserted in order to connect between di erent routing layers. In the 7 nm technology node and beyond, the wire pitch is below 40 nm, and consequently, the vias become very dense, making via layer printing a challenging problem. Recently block copolymer directed self-assembly (DSA) technology has demonstrated great advantages for via layer patterning using guiding templates. To pattern vias with DSA process, guiding templates are usually printed rst with conventional lithography, e:g:, 193 nm immersion lithography (193i) that has a coarser pitch resolution. Then the guiding templates will guide the placement of the DSA patterns (e:g:, vias) inside, and these patterns have a ner resolution than the templates. Di erent template shapes have di erent control on the overlay accuracy of the inside vias. By performing DSA experiments, the guiding templates can be classi ed as feasible and infeasible templates according to the overlay requirement of the technology node. The templates that meet the overlay requirement are feasible templates, and other templates are infeasible. Without considering the DSA template constraints in detailed routing, randomly distributed vias may require infeasible templates to be patterned, which makes the via layers incompatible with the DSA process. In this paper, we propose a DSA-aware detail routing algorithm to optimize the via layers such that only feasible templates are needed for via layer patterning. In addition, among all the feasible templates, the one with better overlay accuracy has higher priority to be picked up by the router for via patterning, which further improves the yield. By enabling DSA process for via layer patterning in the 7 nm technology node, the proposed detailed routing strategy tremendously reduces the manufacturing cost and improves the throughput for IC fabrication.
Directed self-assembly (DSA) technology has already demonstrated its capability for isolated and grouped contact/via pattern for 1D gridded design. If we reverse the resist tune, this technique can also be used to implement the cut printing. However, for this purpose, we need to redistribe the cuts by extending the real wires to form the desired cut distribution for template mask making. Based on this assumption, we propose an algorithm to redistribute the original cuts such that they form groups of non-conflict DSA templates. Experimental results demonstrate that our method can effectively redistribute the cuts and improve the layout manufacturability.