Dr. Zongchang Yu Profile

Dr. Zongchang Yu

Chairman/CTO at Dongfang Jingyuan Electron Ltd

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Publications (13)

Proceedings Article | 10 April 2024 Presentation + Paper

A noval flow of full-chip OPC model calibration and verification by utilizing SEM image contours

Yuan Gan, Changlian Yan, Mengqing Yu, Penghui Zhu, Jing Qiao, Lile Lu, Shengrui Zhang, Ming Ding, Chunying Han, Weijie Shi, Xiaojun Luo, Junhai Jiang, Zongchang Yu

Proceedings Volume 12954, 129540K (2024) https://doi.org/10.1117/12.3010034

KEYWORDS: Optical proximity correction, Calibration, Contour modeling, Scanning electron microscopy, Data modeling, Data acquisition, Contour extraction, Image quality, Critical dimension metrology, Process modeling

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Proceedings Article | 10 April 2024 Poster + Paper

Innovative wafer defect inspection mode: self-adaptive pattern to pattern inspection

Changlian Yan, Jing Qiao, Yuan Gan, Nuo Ding, Zhao Chen, Ming Ding, Xiaojun Luo, Junhai Jiang, Zongchang Yu, Chunying Han

Proceedings Volume 12955, 129552E (2024) https://doi.org/10.1117/12.3010013

KEYWORDS: Inspection, Design, Defect detection, Defect inspection, Scanning electron microscopy, Manufacturing

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Proceedings Article | 28 April 2023 Poster + Paper

Improving FEM wafer review efficiency by introducing different pattern grouping modes

Yuan Gan, Changlian Yan, Rongjia Zhang, Ming Ding, Chunying Han, Junhai Jiang, Zongchang Yu

Proceedings Volume 12495, 124951L (2023) https://doi.org/10.1117/12.2656632

KEYWORDS: Scanning electron microscopy, Semiconducting wafers, Inspection, Design and modelling, Tunable filters, Defect detection, Optical lithography, Optical proximity correction, Wafer inspection, Design for manufacturing

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Proceedings Article | 2 April 2011 Paper

Model-based scanner tuning for process optimization

Rafael Aldana, Venu Vellanki, Wenjin Shao, Ronald Goossens, Zongchang Yu, Xu Xie, Yu Cao, Koen Schreel, Peter Lee, Won Kim, Tjitte Nooitgedagt

Proceedings Volume 7985, 79850L (2011) https://doi.org/10.1117/12.882764

KEYWORDS: Scanners, Semiconducting wafers, Calibration, Critical dimension metrology, Metrology, Optimization (mathematics), Printing, Data modeling, Photomasks, Model-based design

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Proceedings Article | 23 March 2011 Paper

Advanced scanner matching using freeform source and lens manipulators

Jong-Ho Lim, Kyung Kang, Sung-Man Kim, Wenjin Shao, Fei Du, Zhengfan Zhang, Zongchang Yu, John Barbuto, Venu Vellanki, Yu Cao, Ronald Goossens, Seung-Hoon Park, Chris Park, Stefan Hunsche, Junwei Lu

Proceedings Volume 7973, 79732A (2011) https://doi.org/10.1117/12.881680

KEYWORDS: Scanners, Semiconducting wafers, Birefringence, Critical dimension metrology, Diffractive optical elements, Metrology, Cadmium, Fiber optic illuminators, Data modeling, Computational lithography

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Proceedings Article | 23 March 2011 Paper

Scanner matching using pupil intensity control between scanners in 30nm DRAM device

Jongwon Jang, Daejin Park, Jeaseung Choi, Areum Jung, Gyun Yoo, Jungchan Kim, Cheol-kyun Kim, Donggyu Yim, Junwei Lu, Seunghoon Park, Zongchang Yu, Venu Vellanki, Wenkin Shao, Chris Park

Proceedings Volume 7973, 79730S (2011) https://doi.org/10.1117/12.879570

KEYWORDS: Scanners, Critical dimension metrology, Semiconducting wafers, Cadmium, Calibration, Data modeling, Computer simulations, Metrology, Control systems, Lithography

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Proceedings Article | 4 March 2010 Paper

Simulation-based pattern matching using scanner metrology and design data to reduce reliance on CD metrology

Yuan He, Erik Byers, Scott Light, Danielle Hines, Anton Devilliers, Mike Hyatt, Jianming Zhou, Vinay Nair, Zongchang Yu, Yu Cao, Xu Xie, Wenjin Shao, Rafael Aldana, Ronald Goossens, Chang-Qun Ma, Junwei Lu, Hua-yu Liu, Chris Aquino, Peter Engblom, Tjitte Nooitgedagt, Eric Janda

Proceedings Volume 7640, 764014 (2010) https://doi.org/10.1117/12.848255

KEYWORDS: Scanners, Wafer-level optics, Semiconducting wafers, Metrology, Data modeling, Calibration, Critical dimension metrology, Optics manufacturing, Performance modeling, Optical simulations

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Proceedings Article | 30 October 2007 Paper

Production-worthy full chip image-based verification

Zongchang Yu, Youping Zhang, Yanjun Xiao, Wanyu Li

Proceedings Volume 6730, 67300T (2007) https://doi.org/10.1117/12.747022

KEYWORDS: Artificial intelligence, Inspection, Optical proximity correction, Evolutionary algorithms, Printing, Metals, Tolerancing, Feature extraction, Computer simulations, Sensors

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At 65nm technology node and below, with the ever-smaller process window, it is no longer sufficient to apply traditional model-based verification at only the nominal condition. Full-chip, full process-window verification has started to integrate into the OPC flow at the 65nm production as a way of preventing potentially weak post-OPC designs from reaching the mask making step. Through process-window analysis can be done by way of simulating wafer images at each of the corresponding focus and exposure dose conditions throughout the process window using an accurate and predictive FEM model. Alternatively, due to the strong correlation between the post-OPC design sensitivity to dose variation and aerial image (AI) quality, the study of through-dose behavior of the post-OPC design can also be carried out by carefully analyzing the AI. These types of analysis can be performed at multiple defocus conditions to assess the robustness of the post-OPC designs with respect to focus and dose variations. In this paper, we study the AI based approach for post-OPC verification in detail. For metal layer, the primary metrics for verification are bridging, necking, and via coverage. In this paper we are mainly interested in studying bridging and necking. The minimum AI value in the open space gives an indication of its susceptibility to bridging in an over-dosed situation. Lower minimum intensity indicates less risk of bridging. Conversely, the maximum AI between the metal lines provides indication of potential necking issues in an under-dosed situation. At times, however, in a complex 2D pattern area, the location as to where the AI reaches either maximum or minimum is not obvious. This requires a full-chip, dense image-based approach to fully explore the AI profile of the entire space of the design. We have developed such an algorithm to find the AI maximums and minimums that will bear true relevance to the bridging and necking analysis. In this paper, we apply the full-chip image-based analysis to 65nm metal layers. We demonstrate the capturing of potential bridging or necking issues as identified by the AI analysis. Finally, we show the performance of the full-chip image-based verification.

Proceedings Article | 28 June 2005 Paper

Exploring new high speed mask aware RET verification flows

Patrick Martin, Christopher Progler, Young-mog Ham, Bryan Kasprowicz, Rick Gray, James Wiley, Zongchang Yu, Jun Ye

Proceedings Volume 5853, (2005) https://doi.org/10.1117/12.617366

KEYWORDS: Resolution enhancement technologies, Photomasks, Optical proximity correction, Lithography, Manufacturing, Computer simulations, Semiconducting wafers, Inspection, Data modeling, Optical lithography

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Proceedings Article | 17 December 2003 Paper

Investigation of smart inspection of critical layer reticles using additional designer data to determine defect significance

William Volk, Carl Hess, Wayne Ruch, Zongchang Yu, Weimin Ma, Lisa Fisher, Carl Vickery, Z. Mark Ma

Proceedings Volume 5256, (2003) https://doi.org/10.1117/12.518071

KEYWORDS: Inspection, Reticles, Manufacturing, Photomasks, Prototyping, Metals, Semiconducting wafers, System on a chip, Transistors, Yield improvement

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With expected implementation of low k1 lithography on 193nm scanners for 65nm node wafer production, high resolution defect inspection will be needed to insure reticle quality and reticle manufacture process monitoring. Reticle cost and reticle defectivity are both increasing with each shrink to the next node. Simultaneously, system on chip (SoC) designs are increasing in which a large area of the exposure field typically contains dummy patterns and other features which are not electrically active. Knowing which defects will electrically impact device yield and performance can improve reticle manufacturing yield and cycle time -- resulting in lower reticle costs. This investigation examines the feasibility of using additional design data layers for die-to-database reticle inspection to determine in real time the relevance of a reticle defect by its location in the device (Smart InspectionTM). The impact to data preparation and inspection throughput is evaluated. The current prototype algorithm is built on the XPA and XPE die-to-database algorithms for chrome-on-glass and EPSM reticles, respectively. The algorithms implement variable sensitivity based on the additional design data regions. During defect review the defects are intelligently binned into the different predetermined design regions. Tests show the new Smart Inspection algorithm provides the capability of using higher than normal sensitivity in critical regions while reducing sensitivity in less critical regions to filter total defect counts and allow for the review of just defects that matter. Performance characterization of a variable sensitivity Smart Inspection algorithm is discussed in addition to the filtering of the total defect count during review to show the defects that matter to device performance. Using seven critical layer production reticles from a system on chip device we examine the applications of Smart Inspection by layer including active, poly, contact, metal and via layers. Data volume for additional data layers show little impact to inspection data prep time. The total area of the reticle where defects do not matter is as high as 70% on some layers. Review capabilities will be examined for various applications such as reviewing defects in the various regions such as SRAM, dummy pattern, and redundant contact/via specified regions. Lastly, the economics of Smart Inspection will be modeled using the collected knowledge of the applications from the production reticle characterized in this investigation.

Proceedings Article | 2 June 2003 Paper

Energy flux method for inspection of contact and VIA layer reticles

Hector Garcia, William Volk, Yalin Xiong, Sterling Watson, Zongchang Yu, Zhian Guo, Lantian Wang

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.504577

KEYWORDS: Inspection, Reticles, Defect detection, Critical dimension metrology, Semiconducting wafers, Image segmentation, Lithography, Detection and tracking algorithms, Defect inspection, Algorithm development

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Proceedings Article | 27 December 2002 Paper

Simulation-based defect printability analysis on alternating phase-shifting masks for 193-nm lithography

Linyong Pang, Zongchang Yu, Gerard Luk-Pat, Jerry Chen, William Volk

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.468205

KEYWORDS: Photomasks, Semiconducting wafers, Inspection, Lithography, Scanning electron microscopy, Process modeling, Virtual reality, Phase shifts, Cadmium, Defect inspection

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Proceedings Article | 27 December 2002 Paper

Energy flux method for die-to-database inspection of critical layer reticles

Hector Garcia, William Volk, Yalin Xiong, Sterling Watson, Zongchang Yu, Zhian Guo, Lantian Wang

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.468207

KEYWORDS: Inspection, Reticles, Defect detection, Semiconducting wafers, Critical dimension metrology, Photomasks, Lithography, Defect inspection, Databases, Algorithm development

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Showing 5 of 13 publications

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