EUV lithography has enabled shrinking feature sizes up until iN7 using the current Ta-based mask absorber. As we explore next generation nodes, iN5 and beyond, the mask three dimensional (M3D) effects will have a significant impact at wafer level due to the mask architecture, and the oblique illumination angles [1-2]. In order to mitigate these effects, we explore the optical performance of two alternative mask absorber candidates; a High-k absorber and an attenuated phase shifting mask absorber (AttPSM) and compare them to the current Ta-based mask absorber. We evaluate and compare the mask absorbers for memory and logic layers by lithographic source-mask optimization (SMO) using Mentor’s pxSMO tool with ASML’s NXE3400B settings. For memory, contact-holes are simulated using dark-field mask whereas the pillars case is simulated with bright field mask to evaluate bright field as a mask option for EUV with alternative mask absorbers. For logic case, we test these absorbers on iN5 self-aligned block (SAB) layer . The self-aligned block layer is also simulated by adding sub-resolution assist features (SRAFs) to predict the insertion point of SRAFs for logic designs and see if new mask absorber material can reduce the need of SRAF insertion. SMO for memory case shows higher common depth of focus (cDOF) and lower edge placement error (EPE) for High-k absorber over the conventional TaBN mask absorber, whereas significant gain in normalized image log slope (NILS) is observed for the AttPSM absorber. The logic case also has better performance in terms of common depth of focus (cDOF), NILS, EPE mask error enhancement factor (MEEF) and process variation band (PV-band). Adding SRAF’s to iN5 SAB improves the PV-band and image shift through focus for all three cases.
The current industry standard tantalum-based mask absorber (60 nm TaBN) gives strong 3D electromagnetic field (EMF) effects at wafer level, such as shadowing and pitch-dependent best focus shifts. A thinner mask absorber with higher EUV extinction coefficient or a phase shifting mask can mitigate 3D EMF effects . The alternative mask absorber materials would enable further downscaling to foundry 5nm node using state-of-the-art EUV scanners (with 0.33 numerical aperture “NA”) and facilitate future high NA imaging using single exposure. Here we evaluate insertion options on the patterning roadmap for alternative EUV mask absorbers, including high-k absorbers and attenuated phase shifting masks (attPSM) [1-2]. All studies are using relevant designs from foundry N5 logic node. Two alternative mask candidates are compared with the standard TaBN mask. We bring theoretical proof of concept that alternative mask absorber materials generate significant imaging gain in terms of established success criteria. On a set of predefined types of clips (with variations of 1D/2D, horizontal/vertical, dense/isolated patterns), we seek for higher depth of focus (DoF), higher image log slope (ILS), high illumination efficiency (ideally it would be equal to 1), lower pattern shift through focus (i.e., lower tele-centricity errors), lower mask error enhancement factor (MEEF). Source mask optimization (SMO) on N5 logic clip shows a more balanced source and larger common process window for high-k absorber over Ta-based absorber. Using the optical proximity correction (OPC) engine with high-k mask absorber, shows significant gain on overlapping process window (PW), process variation (PV) band, and less line end shortening. Applying advanced Resolution Enhancement Techniques (RET), sub-resolution assist features (SRAFs) on N5 designs demonstrated an improved process in terms of common depth of focus (cDoF), and image shift through focus. It was also observed that the process not using SRAFs with the high-k absorber had superior process window and image shift compared to the Ta-based case with SRAFs. Therefore, adoption of such high-k absorbers could potentially postpone the need for SRAFs.
In advanced technological nodes, the photoresist absorbs light, which is reflected by underlying topography during optical lithography of implantation layers. Anti-reflective coating (ARC) helps to suppress the reflections, but ARC removal may damage transistors, not to mention its relatively high cost. Therefore ARC is usually not used, and topography modeling becomes obligatory for printing implantation shapes. Furthermore, presence of Fin Field Effect Transistors (FinFETs) makes modeling of non-uniform substrate reflections exceptionally challenging.
In realistic designs, the same implantation shape may be found in a vertical or in a rotated horizontal orientation. This creates two types of relationships between the critical dimension (CD) and FinFET, namely parallel to and perpendicular to the fins. The measurement data shows that CDs differ between these two orientations. This discrepancy is also revealed by our Rigorous Optical Topography simulator. Numerical experiments demonstrate that the shape orientation may introduce CD differences of up to 45 nm with a 248 nm illumination for 14 nm technology. These differences are highly dependent on the enclosure (distance between implantation shape and active area). One of the major causes of the differences is that in the parallel orientation the shape is facing solid sidewalls of fins, while the perpendicular oriented shape “sees” only perforated sidewalls of the fin structure, which reflect much less energy.
Meticulously stated numerical experiments helped us to thoroughly understand anisotropic behavior of CD measurement. This allowed us to more accurately account for FinFET-related topography effects in the compact implantation modeling for optical proximity corrections (OPC). This improvement is validated against wafer measurement data.
In a previous work, we demonstrated that the current optical proximity correction model assuming the mask pattern to be analogous to the designed data is no longer valid. An extreme case of line-end shortening shows a gap up to 10 nm difference (at mask level). For that reason, an accurate mask model has been calibrated for a 14-nm logic gate level. A model with a total RMS of 1.38 nm at mask level was obtained. Two-dimensional structures, such as line-end shortening and corner rounding, were well predicted using scanning electron microscopy pictures overlaid with simulated contours. The first part of this paper is dedicated to the implementation of our improved model in current flow. The improved model consists of a mask model capturing mask process and writing effects, and a standard optical and resist model addressing the litho exposure and development effects at wafer level. The second part will focus on results from the comparison of the two models, the new and the regular.
In a previous work  we demonstrated that current OPC model assuming the mask pattern to be analogous to the designed data is no longer valid. Indeed as depicted in figure 1, an extreme case of line-end shortening shows a gap up to 10 nm difference (at mask level). For that reason an accurate mask model, for a 14nm logic gate level has been calibrated. A model with a total RMS of 1.38nm at mask level was obtained. 2D structures such as line-end shortening and corner rounding were well predicted using SEM pictures overlaid with simulated contours. The first part of this paper is dedicated to the implementation of our improved model in current flow. The improved model consists of a mask model capturing mask process and writing effects and a standard optical and resist model addressing the litho exposure and development effects at wafer level. The second part will focus on results from the comparison of the two models, the new and the regular, as depicted in figure 2.
This study quantifies the impact of systematic mask errors on OPC model accuracy and proposes a methodology to reconcile the largest errors via calibration to the mask error signature in wafer data. First, we examine through simulation, the impact of uncertainties in the representation of photomask properties including CD bias, corner rounding, refractive index, thickness, and sidewall angle. The factors that are most critical to be accurately represented in the model are cataloged. CD bias values are based on state of the art mask manufacturing data while other variable values are speculated, highlighting the need for improved metrology and communication between mask and OPC model experts. It is shown that the wafer simulations are highly dependent upon the 1D/2D representation of the mask, in addition to the mask sidewall for 3D mask models. In addition, this paper demonstrates substantial accuracy improvements in the 3D mask model using physical perturbations of the input mask geometry when using Domain Decomposition Method (DDM) techniques. Results from four test cases demonstrate that small, direct modifications in the input mask stack slope and edge location can result in model calibration and verification accuracy benefit of up to 30%. We highlight the benefits of a more accurate description of the 3D EMF near field with crosstalk in model calibration and impact as a function of mask dimensions. The result is a useful technique to align DDM mask model accuracy with physical mask dimensions and scattering via model calibration.
Ionic implantation photolithography step considered to be non critical started to be influenced by unwanted
overexposure by wafer topography with technology node downscaling evolution , . Starting from 2xnm technology
nodes, implant patterns modulated on wafer by classical implant proximity effects are also influenced by wafer
topography which can cause drastic pattern degradation , . This phenomenon is expected to be attenuated by the
use of anti-reflecting coating but it increases process complexity and involves cost and cycle time penalty. As a
consequence, computational lithography solutions are currently under development in order to correct wafer
topographical effects on mask . For ionic implantation source Drain (SD) on Silicon bulk substrate, wafer topography
effects are the consequence of active silicon substrate, poly patterns, STI stack, and transitions between patterned wafer
In this paper, wafer topography aware OPC modeling flow taking into account stack effects for bulk technology
is presented. Quality check of this full chip stack aware OPC model is shown through comparison of mask computational
verification and known systematic defectivity on wafer. Also, the integration of topographical OPC model into OPC
flow for chip scale mask correction is presented with quality and run time penalty analysis.
Reflection by wafer topography and underlying layers during optical lithography can cause unwanted exposure in the resist . This wafer stack effect phenomenon which is neglected for larger nodes than 45nm, is becoming problematic for 32nm technology node and below at the ionic implantation process. This phenomenon is expected to be attenuated by the use of anti-reflecting coating but increases process complexity and adds cost and cycle time penalty. As a consequence, an OPC based solution is today under evaluation to cope with stack effects involved in ionic implantation patterning  . For the source drain (SD) ionic implantation process step on 28nm Fully Depleted Silicon-on-Insulator (FDSOI) technology, active silicon areas, poly silicon patterns, Shallow Trench Isolation (STI), Silicon-on-Insulator (SOI) areas and the transitions between these different regions result in significant SD implant pattern critical dimension variations. The large number of stack variations involved in these effects implies a complex modeling to simulate pattern degradations. This paper deals with the characterization of stack effects on 28nm node using SOI substrates. The large number of measurements allows to highlight all individual and combined stack effects. A new modeling flow has been developed in order to generate wafer stack aware OPC model. The accuracy and the prediction of the model is presented in this paper.
The resolution enhancement through lithography hardware (wavelength and Numerical Aperture) has come to a stop
putting the burden on computational lithography to fill in the resulting gap between design and process until the arrival
of EUV tools. New Computational Lithography techniques such as Optical Proximity Correction (OPC), Sub Resolution
Assist Feature (SRAF), and Lithography Friendly Design (LFD) constitute a significant transformation of the design.
These new Computational Lithography applications have become one of the most computationally demanding steps in
the design process. Computing farms of hundreds and even thousands of CPUs are now routinely used to run these
The 28nm node presents many difficulties due to low k1 lithography whereas the 20nm requires double patterning
solutions. In this paper we present a global view of enhanced RET and DFM techniques deployed to provide a robust
28nm node and prepare for 20nm.
These techniques include advanced OPC manipulation through end user IP insertion into EDA software, optimized sub
resolution assist features (SRAF) placement and pixilated OPC. These techniques are coupled with a fast litho print
check, aka LFD, for 28nm P&R.