A new CMOS current starved voltage controlled ring oscillator (CSVCRO) topology is presented. The proposed voltage
controlled oscillator was designed, analyzed and verified by simulating it in 0.35μm CMOS technology. The VCO
architecture proposed in this work provides high linear relationship between oscillation frequency ranging from 0.7-
1.75GHz over a control voltage ranging from 1.2--2V and results in a large tuning range of 75%. The phase noise
achieved is -88dBc/Hz at an offset frequency of 1MHz. The linear frequency sweep is obtained without employing any
additional compensation techniques resulting in less circuit complexity, die area and power consumption.