In advanced DRAM semiconductor manufacturing, there is a need to reduce the overlay fingerprints. Reducing on device fingerprints with very high spatial frequency remains one of the bottlenecks to achieve sub-2nm on device overlay. After-etch device overlay measurements using the YieldStar in-device metrology (IDM) allow for previously unassessed and uncontrolled fingerprints to be corrected employing higher-order overlay corrections. This is because this technology allows dramatically increased overlay metrology sampling at affordable throughputs. This paper reports considerations for enabling dense after-etch overlay based corrections in a high volume manufacturing environment. Results will be shown on a front end critical layer of SK hynix that has been sampled with IDM with high density wafer sampling, over dozens of lots spanning several weeks.
Introduction and problem statement
Given that EUV lithography allows printing smaller Critical Dimension (CD) features, it can result in non-normal distributed CD populations on ADI wafers [Civay SPIE AL 2014], leading to errors in predicted failure rates [Bristol SPIE AL 2017]. As a result, there is a need to quantify the actual behavior of the CD population extremes by means of massive metrology [Dillen EUVL 2018]. Not only allows this to study the CD distribution, we can in parallel also evaluate pattern quality and the failure mechanisms leading to defects. This massive metrology method provides an accurate failure rate based on CD, and enables new possibilities to define a failure rate based on different metrics in a single measurement.
We analyze the CD uniformity of pillars in polar coordinates using a global waveform based thresholding strategy. In conjunction with this CD information, we also evaluated the print quality of each individual measured feature.
Fig 1. In line detected anomalies and failure definitions
As we gather this information during the measurement of CD, we can limit the additional measurement overhead to neglectable levels.
Application and outlook
We will show how we can leverage this to determine a defect based process window and relations of failure mechanisms through process conditions (see figure 2). When we take failures in a CH dataset into account, we illustrate the effect on the shape of a large dataset distribution in figure 3.
Fig 2. Defect identification for a through exposure dose experiment of pillars. For each condition >13k pillars where measured. The plot clearly shows an asymmetric behavior due to different failure mechanisms at low and high energy. The 2 vertical lines at relative energies 0.93 and 1.05 times nominal indicate the low defect process window.
Fig 3. A distribution of measured regular grid dense CH. The red line is the unfiltered CD data, the blue line is the shape of the distribution after filtering individual CH measurements that have a much lower contrast than expected.
To support the manufacturing of DRAM semiconductors for next and future nodes, there is a constant need to reduce the overlay fingerprints. In this paper we evaluate algorithms which are capable of decoupling wafer deformation from mark deformation and extrapolation effects. The algorithms enable lithography tools to use only the wafer deformation component in the alignment feedforward correction. Therefore improving the (wafer to wafer) overlay. First results will be shared showing improvement of wafer to wafer variation in high-volume manufacturing environment.