Galileo Galilei once quoted: “Measure what is measurable, and make measurable what is not so”. In silicon manufacturing R&D phase, it often happens that engineers would like to access some parameter values that are not easy, even impossible to measure. When looking at a CDSEM image, the parameters of interest seem easy to extract but in practice getting access to them in a robust and reliable way is not always simple. Developing a contour-based metrology tool coupling robust contour extraction with a comprehensive contour metrology environment could help to bridge this gap. In previous works, it has been shown that SEM images contain significant amounts of information that can be extracted and analyzed using efficient contour extraction and analysis toolboxes [1, 2]. Also, the concept of implementing remote contour-based metrology has been introduced. The present work continues to unveil what can be achieved with such solutions. For that, the example of implant layers’ process assumption will be explored. During this process step, counter doping problems can occur for example when the distance between layers deviates from nominal. Therefore, it is crucial for design rule control to measure some critical dimensions such as minimum distance between layers, corner rounding, slope, etc. However, given the characteristics of the different structures in the images, which may come from different layers and/or processes steps, the measurements are not straightforward to extract with standard CDSEM metrology algorithms. Moreover, recipes are complex to setup, measurements by themselves are not very stable, and usually an indirect determination of the key figure is performed. In this paper, we will show that multilayer contour-based metrology, mixing image contour and GDS layout, allows to overcome the previously mentioned difficulties, as well as to generate measurements that are not possible to be performed by using standard algorithms.
In semiconductor fabs, electron microscopes are key equipment for metrology, failure analysis, physical characterization and defect review classification. In a wafer fab like ST Crolles 300mm, CDSEMs are generating more than 20 Million of images per year. The image is by itself a raw material on which the metrology is performed. It is needed to get access to CD which is very often a single value extracted. If the CD is in specification, it is very unlikely that someone will look at the picture. If someone would do so in a systematic way, it would see that there is much more information available in the image than a single CD value. Unfortunately, most of this information passes under the radar of SPC charts and is somehow wasted.
This paper presents results obtained by CDSEM image contour analysis from various kind of technologies and applications in manufacturing in our fab. These results show that images contain significant amounts of information that can be extracted and analyzed using an efficient contour extraction and analysis toolbox.
Process variability of complex shapes can be shown, robust layer to layer metrics can be computed, pattern shifting, shape changes, image quality and many others too. This opens new possibilities for process control and process variability monitoring and mitigation.
The specifications performance data for the latest generation system are compared to prior generations. These results are shown for both missing pattern (or hard) and unknown contamination (or soft) defects of various classifications in different patterns. For hard defects, capability will be demonstrated down to the 65 nm node, with soft defect repair and clean significantly exceeding to even smaller nodes down to 14 nm. The latter is of particular note, especially in the application of the cleaning of fall-on unknown contaminates on pelliclized photomasks. Finally, there will be a discussion of future work to further develop soft repair/clean process and laser processes for other mask technologies.
Process matching is the ability to precisely reproduce the signature of a given fabrication process while using a different one. A process signature is typically described as systematic CD variation driven by feature geometry as a function of feature size, local density or distance to neighboring structures. The interest of performing process matching is usually to address differences in the mask fabrication process without altering the signature of the mask, which is already validated by OPC models and already used in production. The need for such process matching typically arises from the expansion of the production capacity within the same or different mask fabrication facilities, from the introduction of new, perhaps more advanced, equipment to deliver same process of record masks and/or from the re-alignment of processes which have altered over time. For state-of-the-art logic and memory mask processes, such matching requirements can be well below 2nm and are expected to reduce below 1nm in near future. In this paper, a data preparation solution for process matching is presented and discussed. Instead of adapting the physical process itself, a calibrated model is used to modify the data to be exposed by the source process in order to induce the results to match the one obtained while running the target process. This strategy consists in using the differences among measurements from the source and target processes, in the calibration of a single differential model. In this approach, no information other than the metrology results is required from either process. Experimental results were obtained by matching two different processes at Photronics. The standard deviation between both processes was of 2.4nm. After applying the process matching technique, the average absolute difference between the processes was reduced to 1.0nm with a standard deviation of 1.3nm. The methods used to achieve the result will be described along with implementation considerations, to help assess viability for model driven data solutions to play a role in future, critical mask matching efforts.
VSB mask writers, which create patterns using a combination of rectangles and 45 degree triangles, are ill-suited to non-
Manhattan geometries. This issue is particularly acute for layouts which contain a large fraction of curvilinear “offangle”
patterns such as photonic or DRAM designs. Unable to faithfully reproduce the “off-angle” structures, traditional
VSB mask writers approximate the desired design using abutted rectangular shots or small shapes to smooth out line
edge roughness. Fidelity to the original pattern comes at a cost of increased shot count and reduced throughput.
Aselta has developed a novel fracture algorithm to dramatically reduce the shot count of such designs. Using a traditional
VSB pattern generator, the new algorithm provides significant shot count reduction. When combined with a modified
JBX-3200MV VSB, the shot count is reduced while maintaining the same level of fidelity. The data preparation software
tool has also the capability of trading off a more accurate level of fidelity with an even more reduced shot count.
The paper will first describe the basic principles of the fracturing algorithm and e-beam writer hardware configuration
then demonstrate the advantage of the method on a variety of patterns.