Currently advanced MWIR camera systems’ shortcomings are related to 1) their high cost and being proprietary to large aerospace companies, 2) their compromise on power or frame rate, and 3) their compromise on noise and well capacity as the pixel pitch goes down and the array size is increased. This paper presents a novel low SWAP-C commercially available high-end MWIR camera system development. The camera incorporates a 10-micron pitch MWIR FPA with a 3- megapixel array size read out at full motion video rate, and even up to 90Hz rate. The small pitch sensor has various gain modes up to 20 million-electron well capacity as well as low noise at high readout rates delivering full 14-bit performance.
An 8-inch wafer scale process was developed that provides low cost availability of back-side illuminated (BSI) imaging sensors. The process has been optimized to convert standard CMOS and CCD 6-inch or 8-inch wafers from front side illuminated (FSI) sensors to BSI sensors. The process successfully demonstrates wafer planarization, bow correction, bonding to carrier wafers, wafer thinning, re-planarization, anti-reflection coating, through silicon vias (TSVs) and back side metallization. Good wafer thinning control was obtained for a wide range of epi thicknesses varying from 4 microns to 15 microns. The thinner epi is optimized for UV and visible sensing while the thicker epi material is optimized for near-infrared (NIR) sensing. The processed wafers demonstrate backside passivation and anti-reflection (AR) coatings that optimize the QE performance in a variety of bands such as 200nm-300nm, 300nm-400nm and 400nm-900nm.
Proc. SPIE. 11755, Sensors and Systems for Space Applications XIV
KEYWORDS: Signal to noise ratio, Application specific integrated circuits, Sensors, Field programmable gate arrays, Image sensors, Quantization, Analog electronics, Digital electronics, Tolerancing, Temperature metrology
As the number of image sensor output increase the circuit cards and cable designs have become complex and the power unmanageable in space payloads. This paper reports recent ADC integrated circuit (IC) developed for space environment to alleviate the most pressing concerns of the space payload systems. These ADCs are integrated into multi-channel ASICs (4 to 40 per chip) that greatly reducing the system size, weight, power and cost. The ADCs range from 8-bit to 16-bit digitizers with noise approaching the quantization limit while also maintaining ultra-low power dissipation. 14-bit 20 MSPS digitization at 50 mW and 16-bit 250 KSPS for just 5mW is acheived. Novel on the fly programmable architecture, linearity, power dissipation, SNR performance, radiation tolerance and other critical performance parameters are reported. Utility of these ICs is discussed in a wide variety of instruments suitable for LEO, GEO or other orbits.