IC fabs inspect critical masks on a regular basis to ensure high wafer yields. These requalification inspections are costly
for many reasons including the capital equipment, system maintenance, and labor costs. In addition, masks typically
remain in the “requal” phase for extended, non-productive periods of time. The overall “requal” cycle time in which
reticles remain non-productive is challenging to control. Shipping schedules can slip when wafer lots are put on hold
until the master critical layer reticle is returned to production. Unfortunately, substituting backup critical layer reticles
can significantly reduce an otherwise tightly controlled process window adversely affecting wafer yields.
One major requal cycle time component is the disposition process of mask inspections containing hundreds of defects.
Not only is precious non-productive time extended by reviewing hundreds of potentially yield-limiting detections, each
additional classification increases the risk of manual review techniques accidentally passing real yield limiting defects.
Even assuming all defects of interest are flagged by operators, how can any person's judgment be confident regarding
lithographic impact of such defects? The time reticles spend away from scanners combined with potential yield loss due
to lithographic uncertainty presents significant cycle time loss and increased production costs
An automatic defect analysis system (ADAS), which has been in fab production for numerous years, has been improved
to handle the new challenges of 14nm node automate reticle defect classification by simulating each defect’s printability
under the intended illumination conditions. In this study, we have created programmed defects on a production 14nm
node critical-layer reticle. These defects have been analyzed with lithographic simulation software and compared to the
results of both AIMS optical simulation and to actual wafer prints.
Advanced IC fabs must inspect critical reticles on a frequent basis to ensure high wafer yields. These necessary requalification inspections have traditionally carried high risk and expense. Manually reviewing sometimes hundreds of potentially yield-limiting detections is a very high-risk activity due to the likelihood of human error; the worst of which is the accidental passing of a real, yield-limiting defect. Painfully high cost is incurred as a result, but high cost is also realized on a daily basis while reticles are being manually classified on inspection tools since these tools often remain in a non-productive state during classification. An automatic defect analysis system (ADAS) has been implemented at a 20nm node wafer fab to automate reticle defect classification by simulating each defect’s printability under the intended illumination conditions. In this paper, we have studied and present results showing the positive impact that an automated reticle defect classification system has on the reticle requalification process; specifically to defect classification speed and accuracy. To verify accuracy, detected defects of interest were analyzed with lithographic simulation software and compared to the results of both AIMS™ optical simulation and to actual wafer prints.
The fast pace of MOSFET scaling is accelerating the introduction of smaller technology nodes to
extend CMOS beyond 20nm as required by Moore’s law. To meet these stringent requirements, the
industry is seeing an increase in the number of critical layers per reticle set as it move to lower
technology nodes especially in a high volume manufacturing operation. These requirements are
resulting in reticles with higher feature densities, smaller feature sizes and highly complex Optical
Proximity Correction (OPC), built with using new absorber and pellicle materials. These rapid
changes are leaving a gap in maintaining these reticles in a fab environment, for not only haze control
but also the functionality of the reticle. The industry standard of using wet techniques (which uses
aggressive chemicals, like SPM, and SC1) to repel reticles can result in damage to the sub‐resolution
assist features (SRAF’s), create changes to CD uniformity and have potential for creating defects that
require other means of removal or repair. Also, these wet cleaning methods in the fab environment
can create source for haze growth. Haze can be controlled by: 1) Chemical free (dry) reticle cleaning,
2) In‐line reticle inspection in fab, and 3) Manage the environment where reticles are stored. In this
paper we will discuss a dry technique (chemical free) to remove pellicle adhesive residue from
advanced optical reticles. Samsung Austin Semiconductors (SAS), jointly worked with Eco‐Snow
System (a division of RAVE N.P., Inc.) to evaluate the use of Dry Reactive Gas (DRG) technique to
remove pellicle adhesive residue on reticles. This technique can significantly reduce the impact to the
critical geometry in active array of the reticle, resulting in preserving the reticle performance level
seen at wafer level. The paper will discuss results on the viability of this technique used on advanced