In this work, a novel junction profile measurement method is proposed. A serial of junctions were fabricated by B+ implantation. Then a beveled bar which was about 10mm long and several micrometers deep was formed by carefully controlled wet-etching. The remaining depth of n region changes from the full depth that is about 5.3mm after ion implantation to zero depending on its lateral position and the slope of the etching bar. Voltage-current and Laser Beam Induced Current (LBIC) measurements were applied to determine the HgCdTe junction edge. The LBIC signal orrectification characteristic indicates the existence of a PN junction. The junction depth is extracted from the position where the PN junction disappears and the slope of the etching bar. The junction depth of intrinsic doped HgCdTe was measured, which is about 2.4μm. A significant 0.4mm thick N-region was observed. Moreover, junction depths of samples annealed for different time were also investigated. By this method, it’s possible to measure the three dimensional profile of a planar PN junction.
Deposition in thermal ambience can obtain better CdTe passivation layers compared with general evaporation process. HgCdTe infrared focal plane arrays are fabricated to confirm the new process works well. Contrast n+-on-p planar photodiodes are manufactured from the same HgCdTe epilayer. Some use new process while others use general process. The performance of devices using new process shows a significant improvement. The device with general passivation process has a dark current of 7.8×10<sup>-7</sup> A at 50 mV negative bias voltage, and the differential resistance at zero bias is 2.6×10<sup>5</sup> Ω. Meanwhile, the device with new passivation process has a dark current of
1.7×10<sup>-8</sup> A at 50 mV negative bias voltage, and the differential resistance at zero bias is 8.0×10<sup>5</sup> Ω. Moreover, this new heating process provides a better thermal stability. The performance of devices with general passivation process declines after a long time baking at 70 °C. But the performance of the devices with heating passivation process improves a little after a long time baking even at 80 °C. The results show that CdTe deposition by vacuum evaporation in a thermal ambience can make a good HgCdTe surface passivation protection.
A novel, sample junction profile measurement in HgCdTe epilayer is investigated. This measurement is used a scanning
laser microscope to obtain the laser beam induced current (LBIC) signals of photosensitive pixel arrays on a long beveled
HgCdTe epilayer, and the junction profile is extracted from the LBIC data. In this work, junctions are fabricated by B<sup>+</sup>
implantation, and the beveled surface which is about 10mm long and several micrometers deep is formed by wet-etching
way. Because of different epilayer thicknesses on the HgCdTe beveled surface, some n regions of pixels are totally
removed at the deeper side, and the others have residual n regions at the shallower side. Therefore the very position where
the LBIC signal begins to vanish would point out the boundary between junction region and non-junction region, and
then the junction depth is extracted from the boundary data. The lateral sizes of junction at different depths are
determined by the peak-to-peak space in LBIC signals. The junction profile of both Hg vacancies doped and Arsenic
doped HgCdTe was measured in this work. The junction depth is about 1.29μm in Hg vacancy doped HgCdTe and a
significant lateral expansion was observed at low temperature. The junction depth is about 5.48μm in arsenic doped
HgCdTe. Moreover, the new technique is applicable to either HgCdTe or other materials.