Layout context plays a very significant role in printability of layout shapes, and hence it is extremely critical to include layout context information while performing printability checks. In this paper, we are proposing a unique approach of analyzing layout context geometries and use Machine Learning (ML) technique to predict lithography hotspots. Our method uses past lithography simulation results to evaluate geometry margins and profile them in simple geometry rules. The markers of these rules then analyzed by our unique context analyzer and generate data set for train Arterial Neural Network (ANN). Later this trained ANN model used for predictions on new input designs. In this paper, we will also present results to highlight how our approach is better in the accuracy of lithography hotspots detection in comparison to previous work related to pattern matching and machine-learning techniques.
The semiconductor industry has adopted multi-patterning techniques to manage the delay in the extreme ultraviolet lithography technology. During the design process of double-patterning lithography layout masks, two polygons are assigned to different masks if their spacing is less than the minimum printable spacing. With these additional design constraints, it is very difficult to find experienced layout-design engineers who have a good understanding of the circuit to manually optimize the mask layers in order to minimize color-induced circuit variations. In this work, we investigate the impact of double-patterning lithography on analog circuits and provide quantitative analysis for our designers to select the optimal mask to minimize the circuit’s mismatch. To overcome the problem and improve the turn-around time, we proposed our smart “anchoring” placement technique to optimize mask decomposition for analog circuits. We have developed a software prototype that is capable of providing anchoring markers in the layout, allowing industry standard tools to perform automated color decomposition process.
At advanced and mainstream process nodes (e.g., 7nm, 14nm, 22nm, and 55nm process nodes), lithography hotspots can exist in layouts of integrated circuits even if the layouts pass design rule checking (DRC). Existence of lithography hotspots in a layout can cause manufacturability issues, which can result in yield losses of manufactured integrated circuits. In order to detect lithography hotspots existing in physical layouts, pattern matching (PM) algorithms and commercial PM tools have been developed. However, there are still needs to use DRC tools to perform PM operations. In this paper, we propose a PM synthesis methodology, which uses a continuous refinement technique, for the automatic synthesis of a given lithography hotspot pattern into a DRC deck, which consists of layer operation commands, so that an equivalent PM operation can be performed by executing the synthesized deck with the use of a DRC tool. Note that the proposed methodology can deal with not only exact patterns, but also range patterns. Also, lithography hotspot patterns containing multiple layers can be processed. Experimental results show that the proposed methodology can accurately and efficiently detect lithography hotspots in physical layouts.
Proc. SPIE. 10148, Design-Process-Technology Co-optimization for Manufacturability XI
KEYWORDS: Semiconductors, Lithium, Capacitors, Databases, Metals, Error analysis, Silicon, Manufacturing, Transistors, Resistors, Analog electronics, Digital electronics, System on a chip, New and emerging technologies
Analog circuits are sensitives to the changes in the layout environment conditions, manufacturing
processes, and variations. This paper presents analog verification flow with five types of analogfocused
layout constraint checks to assist engineers in identifying any potential device mismatch and
layout drawing mistakes. Compared to several solutions, our approach only requires layout design,
which is sufficient to recognize all the matched devices. Our approach simplifies the data preparation
and allows seamless integration into the layout environment with minimum disruption to the custom
layout flow. Our user-friendly analog verification flow provides the engineer with more confident with
their layouts quality.
Proc. SPIE. 9427, Design-Process-Technology Co-optimization for Manufacturability IX
KEYWORDS: Lithography, Metals, Silicon, Manufacturing, Design for manufacturing, Chemical analysis, Nanoimprint lithography, Failure analysis, Chemical mechanical planarization, Design for manufacturability
DFM rule based scoring is associated with manufacturability rules checking and applying the scoring to predict the yield entitlement for an IC chip design. Achieving high DFM score is one of the key requirements to get high yield. The DFM scoring methodology is currently limited to DFM recommend rules and their associated failure rates. In contrast to failure mechanism, chemical-mechanical polishing (CMP) step topography variations places an important role to it. In this paper, we present an advanced DFM analysis flow to compute DFM score that incorporate topography variation along with recommend rule scoring using complex scoring model to increase silicon yield correlation.