Pattern-based approaches are becoming more common and popular as the industry moves to advanced technology nodes. At the beginning of a new technology node, a library of process weak point patterns for physical and electrical verification are starting to build up and used to prevent known hotspots from re-occurring on new designs. Then the pattern set is expanded to create test keys for process development in order to verify the manufacturing capability and precheck new tape-out designs for any potential yield detractors. With the database growing, the adoption of pattern-based approaches has expanded from design flows to technology development and then needed for mass-production purposes. This paper will present the complete downstream working flows of a design pattern database(PDB). This pattern-based data analysis flow covers different applications across different functional teams from generating enhancement kits to improving design manufacturability, populating new testing design data based on previous-learning, generating analysis data to improve mass-production efficiency and manufacturing equipment in-line control to check machine status consistency across different fab sites.
Systematic yield detractors are normally expected to be identified by ATPG test result diagnostics.
Different test patterns have been designed to test different functions. Test diagnostics can identify
failed functions so that product engineers, based on testing results, can narrow down which block
in the design performs this function. However, it is often hard to narrow down to a more specific
region in a product.
This paper will present a working flow for using design diffing techniques to extract layout
structures and perform a geometry analysis flow combined with testing results to find most
probable suspects that may cause noticeable yield loss.
Silicon testing results are regularly collected for a particular lot of wafers to study yield loss from
test result diagnostics. Product engineers will analyze the diagnostic results and perform a number
of physical failure analyses to detect systematic defects which cause yield loss for these sets of
wafers in order to feedback the information to process engineers for process improvements. Most
of time, the systematic defects that are detected are major issues or just one of the causes for the
overall yield loss.
This paper will present a working flow for using design analysis techniques combined with
diagnostic methods to systematically transform silicon testing information into physical layout
information. A new set of the testing results are received from a new lot of wafers for the same
product. We can then correlate all the diagnostic results from different periods of time to check
which blocks or nets have been highlighted or stop occurring on the failure reports in order to
monitor process changes which impact the yield. The design characteristic analysis flow is also
implemented to find 1) the block connections on a design that have failed electrical test or 2)
frequently used cells that been highlighted multiple times.
Foundries normally receive a large number of designs from different customers every day. It is
desired to automatically profile each incoming design to quantify certain metrics like 1) the
number of polygons per GDS layers 2) what kind of electrical components the design contains 3)
what the dimensions of each electrical component are 4) how frequently any size of components
have been used and their physical locations.
This paper will present a novel method of how to generate a complete profile of components for
any particular design. The component checking flow need to be completed within hours so it will
have very little impact on the tape-out time. A pre-layer checking method is also run to group
commonly used layers for different electrical components and then employ different layout
profiling flows. The foundry does this design chip analysis in order to find potentially weak
devices due to their size or special size requirements for particular electrical components. The
foundry can then take pre-emptive action to avoid yield loss or make an unnecessary mask for
new incoming products before fab processing starts.
It is very well known that as technology nodes move to smaller sizes, the number of design rules
increases while design structures become more regular and the process manufacturing steps have
increased as well. Normal inspection tools can only monitor hard failures on a single layer. For
electrical failures that happen due to inter layers misalignments, we can only detect them through
This paper will present a working flow for using pattern analysis interlayer profiling techniques
to turn multiple layer physical info into group linked parameter values. Using this data analysis
flow combined with an electrical model allows us to find critical regions on a layout for yield
The IC chip manufacturing process is an integrated working flow where after each
manufacturing step, a yield inspection team will apply great effort and machine resources to
inspect and sort through various check points to detect silicon failures. However, despite the
great effort, they cannot efficiently cover a whole chip and cross check all the different layers
and products at the same time.
This paper will present a smart and efficient working flow that can map inspection data
back onto a design and produce more diverse monitor points for inspection, and each set of
monitor points links to a set of statistical design data that shows insight on design structures that
are more sensitive to the process variations. A full-chip post-processing flow is also implemented
to process design layout so that the particular patterns that may cause certain function blocks to
fail can be directly checked on post-processed layout.
Proc. SPIE. 9781, Design-Process-Technology Co-optimization for Manufacturability X
KEYWORDS: Databases, Manufacturing, Profiling, Very large scale integration, Image classification, Acquisition tracking and pointing, Optical proximity correction, Structural design, Electronic design automation, New and emerging technologies, Design for manufacturability
As technology moves towards more advanced nodes, the complexity of VLSI designs continues to grow and unexpected designs in physical layout push the process limits. In the beginning of a new technology node development there are not enough real design chips with complex structures and it is hard for foundries to comprehensively verify their process capabilities. It is necessary for foundries to generate a comprehensive set of test patterns to co-optimize the design rule manual (DRM) and manufacturing process. Furthermore, as the technology goes into an accelerated yield ramp phase, we need to find the potential process weak-points and identify the gaps between the design rules and the process.
This paper will present a novel methodology to enumerate initial test patterns based on other technology node products. With this novel methodology, DRM development and process capability verification can be sped up rapidly in comparison to a more traditional way. At the same time, the process weak-point signatures can be migrated from the older technology nodes to the new technology node for verification. This methodology will help foundries catch process detractor patterns at new technology early development stage.
During a new technology node process setup phase, foundries do not initially have enough product chip designs to conduct exhaustive process development. Different operational teams use manually designed simple test keys to set up their process flows and recipes. When the very first version of the design rule manual (DRM) is ready, foundries enter the process development phase where new experiment design data is manually created based on these design rules. However, these IP/test keys contain very uniform or simple design structures. This kind of design normally does not contain critical design structures or process unfriendly design patterns that pass design rule checks but are found to be less manufacturable. It is desired to have a method to generate exhaustive test patterns allowed by design rules at development stage to verify the gap of design rule and process.
This paper presents a novel method of how to generate test key patterns which contain known problematic patterns as well as any constructs which designers could possibly draw based on current design rules. The enumerated test key patterns will contain the most critical design structures which are allowed by any particular design rule. A layout profiling method is used to do design chip analysis in order to find potential weak points on new incoming products so fab can take preemptive action to avoid yield loss. It can be achieved by comparing different products and leveraging the knowledge learned from previous manufactured chips to find possible yield detractors.
At the advanced technology node, logic design has become extremely complex and is getting more challenging as the pattern geometry size decreases. The small sizes of layout patterns are becoming very sensitive to process variations. Meanwhile, the high pressure of yield ramp is always there due to time-to-market competition. The company that achieves patterning maturity earlier than others will have a great advantage and a better chance to realize maximum profit margins.
For debugging silicon failures, DFT diagnostics can identify which nets or cells caused the yield loss. But normally, a long time period is needed with many resources to identify which failures are due to one common layout pattern or structure. This paper will present a new yield diagnostic flow, based on preliminary EFA results, to show how pattern analysis can more efficiently detect pattern related systematic defects. Increased visibility on design pattern related failures also allows more precise yield loss estimation.
Semiconductor manufacturing technologies are becoming increasingly complex with every passing node. Newer technology nodes are pushing the limits of optical lithography and requiring multiple exposures with exotic material stacks for each critical layer. All of this added complexity usually amounts to further restrictions in what can be designed. Furthermore, the designs must be checked against all these restrictions in verification and sign-off stages. Design rules are intended to capture all the manufacturing limitations such that yield can be maximized for any given design adhering to all the rules. Most manufacturing steps employ some sort of model based simulation which characterizes the behavior of each step. The lithography models play a very big part of the overall yield and design restrictions in patterning. However, lithography models are not practical to run during design creation due to their slow and prohibitive run times. Furthermore, the models are not usually given to foundry customers because of the confidential and sensitive nature of every foundry's processes. The design layout locations where a model flags unacceptable simulated results can be used to define pattern rules which can be shared with customers. With advanced technology nodes we see a large growth of pattern based rules. This is due to the fact that pattern matching is very fast and the rules themselves can be very complex to describe in a standard DRC language. Therefore, the patterns are left as either pattern layout clips or abstracted into pattern-like syntax which a pattern matcher can use directly. The patterns themselves can be multi-layered with "fuzzy" designations such that groups of similar patterns can be found using one description. The pattern matcher is often integrated with a DRC tool such that verification and signoff can be done in one step. The patterns can be layout constructs that are "forbidden", "waived", or simply low-yielding in nature. The patterns can also contain remedies built in so that fixing happens either automatically or in a guided manner. Building a comprehensive library of patterns is a very difficult task especially when a new technology node is being developed or the process keeps changing. The main dilemma is not having enough representative layouts to use for model simulation where pattern locations can be marked and extracted. This paper will present an automatic pattern library creation flow by using a few known yield detractor patterns to systematically expand the pattern library and generate optimized patterns. We will also look at the specific fixing hints in terms of edge movements, additive, or subtractive changes needed during optimization. Optimization will be shown for both the digital physical implementation and custom design methods.
Advanced process nodes introduce new variability effects due to increased density, new material, new device structures, and so forth. This creates more and stronger Layout Dependent effects (LDE), especially below 28nm. These effects such as WPE (Well Proximity Effect), PSE (Poly Spacing Effect) change the carrier mobility and threshold voltage and therefore make the device performances, such as Vth and Idsat, extremely layout dependent. In traditional flows, the impact of these changes can only be simulated after the block has been fully laid out, the design is LVS and DRC clean. It’s too late in the design cycle and it increases the number of post-layout iteration. We collaborated to develop a method on an advanced process to embed several LDE sources into a LDE kit. We integrated this LDE kit in custom analog design environment, for LDE analysis at early design stage. These features allow circuit and layout designers to detect the variations caused by LDE, and to fix the weak points caused by LDE. In this paper, we will present this method and how it accelerates design convergence of advanced node custom analog designs by detecting early-on LDE hotspots on partial or fully placed layout, reporting contribution of each LDE component to help identify the root cause of LDE variation, and even providing fixing guidelines on how to modify the layout and to reduce the LDE impact.