In a sub 2Xnm node process, the feedback of pattern weak points is more and more significant. Therefore, it is very important to extract the systemic defect in Double Patterning Technology(DPT), however, it is impossible to predict exact systemic defect at the recent photo simulation tool. Therefore, the method of Process Window Qualification (PWQ) is very serious and essential these days.
Conventional PWQ methods are die to die image comparison by using an e-beam or bright field machine. Results are evaluated by the person, who reviews the images, in some cases. However, conventional die to die comparison method has critical problem. If reference die and comparison die have same problem, such as both of dies have pattern problems, the issue patterns are not detected by current defect detecting approach. Aside from the inspection accuracy, reviewing the wafer requires much effort and time to justify the genuine issue patterns. Therefore, our company adopts die to data based matching PWQ method that is using NGR machine. The main features of the NGR are as follows. First, die to data based matching, second High speed, finally massive data were used for evaluation of pattern inspection. Even though our die to data based matching PWQ method measures the mass data, our margin decision process is based on image shape. Therefore, it has some significant problems.
First, because of the long analysis time, the developing period of new device is increased. Moreover, because of the limitation of resources, it may not examine the full chip area. Consequently, the result of PWQ weak points cannot represent the all the possible defects. Finally, since the PWQ margin is not decided by the mathematical value, to make the solid definition of killing defect is impossible.
To overcome these problems, we introduce a statistical values base process window qualification method that increases the accuracy of process margin and reduces the review time. Therefore, it is possible to see the genuine margin of the critical pattern issue which we cannot see on our conventional PWQ inspection; hence we can enhance the accuracy of PWQ margin.
It is increasingly difficult to determine degree of completion of the patterning and the distribution at the DRAM Cell Patterns. When we research DRAM Device Cell Pattern, there are three big problems currently, it is as follows. First, due to etch loading, it is difficult to predict the potential defect. Second, due to under layer topology, it is impossible to demonstrate the influence of the hotspot. Finally, it is extremely difficult to predict final ACI pattern by the photo simulation, because current patterning process is double patterning technology which means photo pattern is completely different from final etch pattern. Therefore, if the hotspot occurs in wafer, it is very difficult to find it.
CD-SEM is the most common pattern measurement tool in semiconductor fabrication site. CD-SEM is used to accurately measure small region of wafer pattern primarily. Therefore, there is no possibility of finding places where unpredictable defect occurs. Even though, "Current Defect detector" can measure a wide area, every chip has same pattern issue, the detector cannot detect critical hotspots. Because defect detecting algorithm of bright field machine is based on image processing, if same problems occur on compared and comparing chip, the machine cannot identify it. Moreover this instrument is not distinguished the difference of distribution about 1nm~3nm. So, "Defect detector" is difficult to handle the data for potential weak point far lower than target CD.
In order to solve those problems, another method is needed. In this paper, we introduce the analysis method of the DRAM Cell Pattern Hotspot.
Starting with the sub 2Xnm node, the process window becomes smaller and tighter than before. Pattern related error budget is required for accurate critical-dimension control of Cell layers. Therefore, lithography has been faced with its various difficulties, such as weird distribution, overlay error, patterning difficulty etc. The distribution of cell pattern and overlay management are the most important factors in DRAM field. We had been experiencing that the fatal risk is caused by the patterns located in the tail of the distribution. The overlay also induces the various defect sources and misalignment issues. Even though we knew that these elements are important, we could not classify the defect type of Cell patterns. Because there is no way to gather massive small pattern CD samples in cell unit block and to compare layout with cell patterns by the CD-SEM. The CD- SEM is used in order to gather these data through high resolution, but CD-SEM takes long time to inspect and extract data because it measures the small FOV. (Field Of View) However, the NGR(E-beam tool) provides high speed with large FOV and high resolution. Also, it’s possible to measure an accurate overlay between the target layout and cell patterns because they provide DBM. (Design Based Metrology) By using massive measured data, we extract the result that it is persuasive by applying the various analysis techniques, as cell distribution and defects, the pattern overlay error correction etc. We introduce how to correct cell pattern, by using the DBM measurement, and new analysis methods.
As semiconductor process technology scales down to sub 30nm process node and beyond dimensions, the
printability and process window of the lithographic patterns are seriously reduced due to the fundamental
limit of the lithography and process variations.
In this paper, we introduce a various analysis methodology of pattern variability for higher device
performance using with applications of DBV (Design Based Verification).
Pattern variability is affected by both pattern process margins and electrical margins such as distribution of
Even if post lithography verification would carry out after model based OPC, Pattern variability is increased
not only unpredictable OPC hotspots but also unanticipated hotspots by AEI loading skew in full-chip. Secondly, electrical hotspots which are extracted by tail distributions of gate length are not always reliable enough to represent critical path with gate length of full-chip. We constructed New OCV extraction flow with a full-chip pattern classification that is required for both gate distribution accuracy and analysis of gate tail patterns. In this report, we investigated about the relationship between a pattern feature and pattern distribution of transistor length.
Semiconductor industry has been experiencing rapid and continuous shrinkage of feature size along with Moore's law.
As the VLSI technology scales down to sub 40nm process node. Control of critical dimension (CD) and Extraction of
Unanticipated weak point pattern effects known as "hot spots" becoming more challenging and difficult.
Therefore, experimental full-chip inspection methodologies for Control of critical dimension (CD) and hotspots
extraction are necessary in order to reduce Turn-Around-Time (TAT) for steep ramp up Manufacture.
In this paper, we introduce the concepts of an innovative reduction Turn-around-time (TAT) in manufacture production
with applications of DBV (Design Based Verification).
The noble methodologies employed by our own technology with application of DBV are highly advantageous for exactly
determining for process judgment go or no-go about wafer process in mass-production of memory device.
Defect is a killing factor in photomask fabrications. For 65nm node photomask fabrication, even smaller than 1 um particle can cause hard-to-repair defect. And it is not easy to find the defect source and solve it. For this reason, the process monitoring system that shows us current defect trend rapidly and effectively is highly required. At the same time, this system can be used for verifying the process stability and detecting unusual signals in process.