Machine learning (ML) techniques have been applied for quick optical proximity correction (OPC) processing. A key limitation of previous ML-OPC approaches lies in the fact that a layout segment is corrected while the correction result for other segments is not reflected yet. Bidirectional recurrent neural network (BRNN) model is adopted in this paper to alleviate this problem. BRNN consists of multiple neural network instances, which are serially linked through hidden layer connections in both forward- and backward-directions. Each instance corresponds to one layout segment, so BRNN processing corrects a group of nearby segments together. Two key problems are identified and addressed: mapping between layout segments and neural network instances, and network input features. In experiments, BRNN-OPC achieves 3.9nm average EPE for test M1 layout, which can be compared to 6.7nm average EPE from state-of-the-art ML-OPC method.
As the minimum feature size continues to shrink down, the interconnect resistance is getting more important. The wire RC delay now often limits the overall chip performance. In this paper, we address a wire width optimization in self-aligned double patterning (SADP) process, where wire widening and double via insertion are considered simultaneously to minimize the total wire delay of timing critical paths. For each of the wires on the critical paths, the candidate directions to which we enlarge the wire is identified while design rules are taken into account. Each candidate direction is then evaluated in terms of the potential wire delay reduction. We finally select an optimal widening configuration by reducing the problem into a minimum weight independent set (MWIS), which is solved by using an integer learning programming (ILP) solver. Experiments are conducted for a few test circuits; wire resistance is reduced by 22.4%, on average, which allows the clock period to be reduced by 12.5%.
Redundant via (RV) insertion is employed to enhance via manufacturability, and has been extensively studied. Self-aligned double patterning (SADP) process, brings a new challenge to RV insertion since newly created cut for each RV insertion has to be taken care of. Specifically, when a cut for RV, which we simply call RV-cut, is formed, cut conflict may occur with nearby line-end cuts, which results in a decrease in RV candidates. We introduce cut merging to reduce the number of cut conflicts; merged cuts are processed with stitch using litho-etch-litho-etch (LELE) multi-patterning method. In this paper, we propose a new RV insertion method with cut merging in SADP for the first time. In our experiments, a simple RV insertion yields 55.3% vias to receives RVs; our proposed method that considers cut merging increases that number to 69.6% on average of test circuits.
Self-aligned double patterning (SADP) has been proposed as an alternative patterning solution for sub-10nm technology because of delay of advanced lithography beyond 193nm ArF. In conventional SADP, line and space style of dummy metal fills are inserted once main design is complete. A large buffer distance is required around the main design because no further verification of main design (in presence of fills) is performed. This causes irregular pattern density, which becomes a source of process variations. We propose integrated-fill, in which main design and dummy fill insertion are performed together. This requires a change in overall design flow, which we discuss. Integrated-fill is demonstrated in M2 layer of SADP process; M2 density increases by 15.7% with 2.3% reduction in standard deviation of density distribution; metal thickness variation is also reduced by 24%. More dummy fills cause increased coupling capacitance, which however is shown to be insignificant.