Power on reset circuit provides a reset signal for the entire system into normal working condition. When power reaches normal operating voltage and remains stable, power on reset circuit provides one rectangular pulse signal which has a steep edge for the digital baseband part of the tag. After reset, POR circuit is isolated with the follow-up circuits, having good stability. In this paper, we designed two new static ultra-low power consumption power-on reset circuits. The first circuit uses Schmitt triggers for signal threshold detection and a certain delay. The peak current of the first circuit is 31uA, with a static current being 33 pA. The second circuit is based on a clamp circuit and PMOS gate cross-coupled circuit which greatly reduces the static current (190 pA). And the peak current of the second circuit is 21 μA.
An 8Mb phase change random access memory (PCRAM) has been developed by a 130nm 4-ML standard CMOS technology based on the Resistor-on-Via-stacked-Plug (RVP) storage cell structure. This phase change resistor is formed after CMOS logic fabrication. PCRAM can be embedded without changing any logic device and process. The memory cell selector is implemented by a standard 1.2V NMOS device. Aimed at the resistance distributions, lowering the operation current and improving the bit yield, some methods are used to optimize the design of the chip.
A serial peripheral interface (SPI) 16-Kbit phase change memory chip based on 0.13μm CMOS process is designed. It contains a parallel error correcting code (ECC) circuit, which can correct 2 bits in every 8 bits without clock delay, enabling the write and read operations performed at bus speed. All the data transfers in 8-bit groups and can be read or written with write protection scheme by unlimited cycle, in which address can automatically increase one by one. Simulation results show that the chip can work correctly in SPI mode and with ECC scheme. It is now under testing.