A 13.5 Mhz Single Chip Multiformat Discrete Cosine Transform

F. Jutand; N. Demassieux; M. Dana; J-P . Durandeau; G. Concordel; A. Artieri; E. Mackowiack; L. Bergher

doi:10.1117/12.976478

13 October 1987 A 13.5 MHz Single Chip Multiformat Discrete Cosine Transform

F. Jutand, N. Demassieux, M. Dana, J-P . Durandeau, G. Concordel, A. Artieri, E. Mackowiack, L. Bergher

Proceedings Volume 0845, Visual Communications and Image Processing II; (1987) https://doi.org/10.1117/12.976478
Event: Cambridge Symposium on Optics in Medicine and Visual Image Processing, 1987, San Diego, CA, United States

Abstract

This communication presents a 2D Discrete Cosine Transform Processor realized with a single chip. Implementing a B.G Lee graph, it can perform DCT computation at the video rate of 13.5 MHz on blocks of a programmable size, from 16*16 to 4*4. Direct or inverse DCT computation is also programmable. The maximum computation error for a direct transform followed by an inverse transform is always better than 1 LSB. A hardwired, mapped architecture has led to a 39 mm2 silicon area for a 1.25μ CMOS 2-metal process.

Citation Download Citation

F. Jutand, N. Demassieux, M. Dana, J-P . Durandeau, G. Concordel, A. Artieri, E. Mackowiack, and L. Bergher "A 13.5 MHz Single Chip Multiformat Discrete Cosine Transform", Proc. SPIE 0845, Visual Communications and Image Processing II, (13 October 1987); https://doi.org/10.1117/12.976478

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