Recent Advances In Z-Technology Architecture

David Ludwig; Daryl Smetana; Stuart Shanken

doi:10.1117/12.960376

13 September 1989 Recent Advances In Z-Technology Architecture

David Ludwig, Daryl Smetana, Stuart Shanken

Proceedings Volume 1097, Materials, Devices, Techniques, and Applications for Z-Plane Focal Plane Array; (1989) https://doi.org/10.1117/12.960376
Event: SPIE 1989 Technical Symposium on Aerospace Sensing, 1989, Orlando, FL, United States

Abstract

Z-technology utilizes the process of stacking integrated circuits (ICs) to achieve a high degree of packaging density. This technique has been most commonly applied to packaging read out electronics for infrared (IR) focal plane arrays to achieve more signal processing at the detector interface. Irvine Sensor Corporation's (ISC's) standard packaging technology, called HYMOSS (HYbrid Mosaic On Stacked Silicon), has been tailored for stacking 0.004- inch thick silicon integrated circuits of custom designed read out electronics. New advances have been made which allow for stacking; non-silicon ICs, commercial (non-custom) circuits, and/or ICs which have been thinned to 0.002 inches.

Citation Download Citation

David Ludwig, Daryl Smetana, and Stuart Shanken "Recent Advances In Z-Technology Architecture", Proc. SPIE 1097, Materials, Devices, Techniques, and Applications for Z-Plane Focal Plane Array, (13 September 1989); https://doi.org/10.1117/12.960376

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