Wafer-level integration for hybrid chip of infrared detectors

J. O. Son; S. Y. Na; Y H. Kim; H. J. Lee; J. Jung

doi:10.1117/12.2663751

13 June 2023 Wafer-level integration for hybrid chip of infrared detectors

J. O. Son, S. Y. Na, Y H. Kim, H. J. Lee, J. Jung

Proceedings Volume 12534, Infrared Technology and Applications XLIX; 125341Y (2023) https://doi.org/10.1117/12.2663751
Event: SPIE Defense + Commercial Sensing, 2023, Orlando, Florida, United States

Abstract

A large format, high density integration, high-performance infrared detectors are used in a wide range of imaging applications. However, it is difficult to fabricate a hybrid chip of a high performance infrared detector because of the low flip-chip bonding and under-fill process yields. In this work, the large format hybrid chip fabrication process with wafer level integration schemes is presented. In particular, the structure of the fabricated hybrid chip and the method of fabrication a hybrid chip by Au-to-Au bonding. Finally, the result of a hybrid chip made of pixel pitch 20μm is presented.

Citation Download Citation

J. O. Son, S. Y. Na, Y H. Kim, H. J. Lee, and J. Jung "Wafer-level integration for hybrid chip of infrared detectors", Proc. SPIE 12534, Infrared Technology and Applications XLIX, 125341Y (13 June 2023); https://doi.org/10.1117/12.2663751

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