This paper discusses a layout of bus-on-chip core referring to SoC thinking which is composed of six sections based on a
physical chip of FPGA: multi-Processor cache coherence unit, external bus control module, TT&C module, Ethernet
Mac interface, EDAC/DMA module, and AMBA bridges. Multi-processor cache coherence unit, as a key part of the bus
core, is used to serve the rapid parallel computing by means of the breakthrough of write/read speed of EMS memory
and enhances the reliability of OBC with the service of supporting the hot standby of redundancy and the reconfiguration
of fault-tolerance. External bus control module is made to support the PnP of external components applying varieties of
buses, which is designed by means of soft-core in order to adapt the variation of macro-design and improve the
flexibility of external application. TT&C module is the interface of subsystems of telemetry, telecommand and
communication, which involves the protocols of HDLC. Ethernet Mac interface based on TCP/IP acts as the access of
ISL for formation flying, constellation, etc. EDAC/DMA module mainly manages the data exchange between AMBA
bus and RAM, and assigns DMA for the payloads.
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