The use of a physical guard ring in CMOS single-photon avalanche diodes (SPADs) based on n⁺/(deep)p-well and p⁺/(deep)n-well structures is a common solution to control the electric field of the SPADs periphery and prevent the premature lateral breakdown. However, this leads to a decrease of the detection efficiency, i.e., the fill-factor, especially when the SPADs size is reduced. Our paper presents an experimental and simulation study on replacing the physical guard ring by a virtual guard ring to improve the fill-factor and the scalability of a n⁺  /  p-well SPAD implemented in 0.35-μm pin-photodiode CMOS technology. Accordingly, the optimization of the virtual guard ring and its superiority at downscaling are discussed, and the SPAD scalability in size with respect to the fill-factor is quantified in this technology.