Presentation + Paper
28 April 2023 A holistic approach to zero defect products when wafer fab does not output zero defects
Author Affiliations +
Abstract
The growth of applications in the automotive space including safety, security, driving assist, vehicle dynamics, networking, etc. is driving exponential demand for superior quality semiconductor products in the vehicle. This carries a serious responsibility for suppliers, as automakers expect quality that can be measured on a defective parts per billion scale (DPPB). Orthogonal to this is the continued aggressively shrinking technology roadmap supporting the new advanced finFET nodes, where exponentially complex processing is creating limitations in Design for Manufacturing needed to achieve Zero Defect products. Additionally, increased product complexity and higher number of product features can lead to lower observability requiring new thinking to detect, accelerate, and prevent escape. This paper explains the challenges and new solutions to delivering products at these strict automotive required intrinsic and extrinsic quality levels, all while at an acceptable product cost. Using real world case studies, it highlights advances in innovative test methods deployed to target “time zero” (T0) random and systemic defects, and Design for Stress and Advanced Outlier Detection techniques used to activate, then screen potentially “latent defects” during factory testing. The paper illustrates why there is no single silver bullet that can deliver ZD product quality in advanced nodes, instead it is necessary that industry experts from fields such as process technology, design, product, test and quality teams, collaborate on and co-deliver complementary process, design and test solutions to achieve the ever-increasing demands for quality in the industry.
Conference Presentation
© (2023) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Stephen R. Traynor and Jesse Yanez "A holistic approach to zero defect products when wafer fab does not output zero defects", Proc. SPIE 12495, DTCO and Computational Patterning II, 1249515 (28 April 2023); https://doi.org/10.1117/12.2660135
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KEYWORDS
Semiconducting wafers

Semiconductors

Silicon

Design and modelling

Yield improvement

Industry

Manufacturing

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