CONFERENCE PROCEEDINGS
Advanced Search
Home > Proceedings > Volume 5117 > Article
Open Access Paper
21 April 2003 High-bandwidth low-latency global interconnect
Christer M Svensson, Peter Caputa
Author Affiliations +
Proceedings Volume 5117, VLSI Circuits and Systems; (2003) https://doi.org/10.1117/12.499957
Event: Microtechnologies for the New Millennium 2003, 2003, Maspalomas, Gran Canaria, Canary Islands, Spain
Abstract
Global interconnects have been identified as a serious limitation to chip scaling, due to their limited bandwidth and large delay. A critical analysis of intrinsic limitations of electrical interconnect indicates that these limitations can be overcome. This basic analysis is presented, together with design constraints. We demonstrate a scheme for this, based on the utilization of upper-level metals as transmission lines. A global communication architecture based on a global mesochronous, local synchronous approach allows very high data-rate per wire and therefore very high bandwidth in buses of limited width. As an example, we demonstrate a 320μm wide bus with a capacity of 160Gb/s in a nearly standard 0.18μm process.
© (2003) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Citation Download Citation
Christer M Svensson and Peter Caputa "High-bandwidth low-latency global interconnect", Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); https://doi.org/10.1117/12.499957
PROCEEDINGS
 9 PAGES
DOWNLOAD PAPER SAVE TO MY LIBRARY
GET CITATION
Lens.org Logo
CITATIONS
Cited by 6 scholarly publications.
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Metals
Skin
Network on a chip
Signal attenuation
Clocks
Dielectrics
Performance modeling
RELATED CONTENT
Subscribe to Digital Library
Receive Erratum Email Alert
Back to Top