Application of clock gating techniques at a flip-flop level to switching noise reduction in VLSI circuits

Pilar Parra; Javier Castro; Manuel Valencia; Antonio J. Acosta

doi:10.1117/12.608276

30 June 2005 Application of clock gating techniques at a flip-flop level to switching noise reduction in VLSI circuits

Pilar Parra, Javier Castro, Manuel Valencia, Antonio J. Acosta

Proceedings Volume 5837, VLSI Circuits and Systems II; (2005) https://doi.org/10.1117/12.608276
Event: Microtechnologies for the New Millennium 2005, 2005, Sevilla, Spain

Abstract

One of the most important sources of switching noise in large VLSI circuits is the clock-driven circuitry, meaning that memory elements are the main source of noise in digital circuits. This paper faces the application of clock-gating, a well known low-power technique, to the reduction of switching-noise generation. Sources of switching noise in master-slave flip-flops will be analyzed. It will be shown how different solutions for the clock-gated logic show very different results regarding switching-noise generation. Illustrative examples characterized through HSPICE simulations, as well as the application of clock-gating to 16-bit synchronous counter as demonstrator, will provide useful design guidelines for reduction of switching noise generation.

Citation Download Citation

Pilar Parra, Javier Castro, Manuel Valencia, and Antonio J. Acosta "Application of clock gating techniques at a flip-flop level to switching noise reduction in VLSI circuits", Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); https://doi.org/10.1117/12.608276

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