Modeling and design of high-order phase locked loops

Brian Daniels; Gerard Baldwin; Ronan Farrell

doi:10.1117/12.608485

30 June 2005 Modeling and design of high-order phase locked loops

Brian Daniels, Gerard Baldwin, Ronan Farrell

Proceedings Volume 5837, VLSI Circuits and Systems II; (2005) https://doi.org/10.1117/12.608485
Event: Microtechnologies for the New Millennium 2005, 2005, Sevilla, Spain

Abstract

In this paper a new stable high order Digital Phase Lock Loop (DPLL) design technique is proposed. PLLs of order greater than two display better noise bandwidth, B_l, than classical second order PLLs. However these are not unconditionally stable as in the second order case. This technique uses linear theory to design the DPLL. The stability of the DPLL is guaranteed by placing a restriction on the system gain. This stability boundary is found by transforming the system transfer function to the Z-domain and plotting the root locus of the LPLL for values of gain where all the system poles lie inside the unit circle. The minimum value of gain where all the poles lie inside the unit circle forms the stability boundary. It is shown that the stability boundary of the LPLL is comparable to the stability boundary of the DPLL. Finally where the above filter design system produces slow lock, gear shifting of the DPLL components is considered. This allows the DPLL to start off with a wide loop bandwidth and switch to the narrow bandwidth once the system has locked.

Citation Download Citation

Brian Daniels, Gerard Baldwin, and Ronan Farrell "Modeling and design of high-order phase locked loops", Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); https://doi.org/10.1117/12.608485

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