A study of overlay mark robustness and enhanced alignment techniques for alignment improvement on metal layers of sub-100-nm technology

Kaushalia Dubey; Toru Nakamura; Hiroshi Tanaka; Nozomu Hayashi; Shinichi Egashira; Kazuhiko Mishima; Tomohiro Mase; Tamio Takeuchi; Akihiko Honda; Takatoshi Kakizaki

doi:10.1117/12.711324

26 March 2007 A study of overlay mark robustness and enhanced alignment techniques for alignment improvement on metal layers of sub-100nm technology

Kaushalia Dubey, Toru Nakamura, Hiroshi Tanaka, Nozomu Hayashi, Shinichi Egashira, Kazuhiko Mishima, Tomohiro Mase, Tamio Takeuchi, Akihiko Honda, Takatoshi Kakizaki

Author Affiliations +

Proceedings Volume 6520, Optical Microlithography XX; 652033 (2007) https://doi.org/10.1117/12.711324
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

The rapid advancement in lithography and continuing shrink in feature dimensions demand tighter overlay tolerances for fabrication of memory circuits with higher yields (Refer to table 1 for ITRS overlay requirements). To meet tight overlay tolerances, sources of alignment errors need to be identified and corrected accurately. Alignment errors can be contributed by 3 factors; wafer induced shift (WIS), tool induced shift (TIS) and WIS-TIS interaction. WIS is introduced by wafer processing while TIS is introduced by the alignment tool (i.e. scanner or metrology). This paper introduces methods for improvement of alignment performance at layers that experience WIS. A study on mark reflectivity was done. A number of various alignment mark designs were evaluated. The most robust mark to Tungsten Chemical Mechanical Polishing (WCMP) process, based on experimental results, will be illustrated. The concept of the 'Alignment Parameter Optimizer' to select the best alignment illumination mode for each mark and the best sample shots for alignment within the wafer, taking throughput into consideration, will be discussed. A new alignment algorithm that is able to compensate for asymmetric alignment marks will also be presented in this paper. Finally, production data from a Dynamic Random Access Memory (DRAM) manufacturer with the implementation of the above-mentioned concepts will be illustrated.

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Kaushalia Dubey, Toru Nakamura, Hiroshi Tanaka, Nozomu Hayashi, Shinichi Egashira, Kazuhiko Mishima, Tomohiro Mase, Tamio Takeuchi, Akihiko Honda, and Takatoshi Kakizaki "A study of overlay mark robustness and enhanced alignment techniques for alignment improvement on metal layers of sub-100nm technology", Proc. SPIE 6520, Optical Microlithography XX, 652033 (26 March 2007); https://doi.org/10.1117/12.711324

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