Paper
4 December 2008 A cost effective spin on sidewall material alternative to the CVD sidewall process
Daisuke Maruyama, Bang-Ching Ho, Sangwoong Yoon, Rikimaru Sakamoto, Yasushi Sakaida, Keisuke Hashimoto, Noriaki Fujitani, Hiroaki Yaguchi, Koutastu Matsubara
Author Affiliations +
Proceedings Volume 7140, Lithography Asia 2008; 714037 (2008) https://doi.org/10.1117/12.804490
Event: SPIE Lithography Asia - Taiwan, 2008, Taipei, Taiwan
Abstract
193nm immersion and Hyper NA lithography are used at 45nm and beyond. The next generation of lithography will use a new technology such as Double Pattering, EUV or EB. Double patterning is one of the currently acceptable technologies. Three common double pattern techniques are Litho-Etch-Litho-Etch (LELE), freezing, and sidewall (spacer) process. From a technical standpoint LELE is a very promising process, except for the second litho alignment. However, the cost of ownership will be very high because LELE will cost about twice as much as the current single litho patterning process. In order to build up a suitable double patterning technique, many device makers are developing unique processes. Two of these processes are freezing and sidewall. Flash memory makers are diligently investigating the sidewall process by CVD. This is because of the lack of a second litho alignment step, even with its high cost. The high cost of the CVD process can be reduced if a spin on material is used. One of the goals of this paper is to reduce the cost of ownership by using spin on coatings for the sidewall process. Currently we are investigating this approach to control the sidewall width, profile and other properties.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Daisuke Maruyama, Bang-Ching Ho, Sangwoong Yoon, Rikimaru Sakamoto, Yasushi Sakaida, Keisuke Hashimoto, Noriaki Fujitani, Hiroaki Yaguchi, and Koutastu Matsubara "A cost effective spin on sidewall material alternative to the CVD sidewall process", Proc. SPIE 7140, Lithography Asia 2008, 714037 (4 December 2008); https://doi.org/10.1117/12.804490
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KEYWORDS
Silicon

Thin film coatings

Chemical vapor deposition

Ultraviolet radiation

Double patterning technology

Lithography

Semiconducting wafers

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