Resolution Enhancement Techniques and Design for Manufacturability: Containing and Accounting for Variabilities in Integrated Circuit Creation

Alfred K. K. Wong

doi:10.1117/1.2784723

1 July 2007 Resolution Enhancement Techniques and Design for Manufacturability: Containing and Accounting for Variabilities in Integrated Circuit Creation

Alfred K. K. Wong

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Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol. 6, Issue 3, 031001 (July 2007). https://doi.org/10.1117/1.2784723

This PDF file contains the editorial “Resolution Enhancement Techniques and Design for Manufacturability: Containing and Accounting for Variabilities in Integrated Circuit Creation” for JM3 Vol. 6 Issue 03

©(2007) Society of Photo-Optical Instrumentation Engineers (SPIE)

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Alfred K. K. Wong "Resolution Enhancement Techniques and Design for Manufacturability: Containing and Accounting for Variabilities in Integrated Circuit Creation," Journal of Micro/Nanolithography, MEMS, and MOEMS 6(3), 031001 (1 July 2007). https://doi.org/10.1117/1.2784723

Published: 1 July 2007

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