2.1.

Samples and Experimental Characterization

The focus of this work is to study the effect of the EIC-PIC 3D assembly on the thermal performance of the PIC, so the experimental test vehicle is limited to these components (Fig. 2). In this figure, the PIC is visible, with the EIC flip-chipped¹³ on top. In Fig. 2(c), a cross section is shown of the 3D interconnect between the two dies, which consists of a $50\mu \mathrm{m}$ pitch Cu-Sn $\mu \mathrm{bump}$ array and an epoxy-based underfill material. The PIC die size is $5\times 5\mathrm{m}{\mathrm{m}}^2$, and the EIC die size is $1.5\times 1\mathrm{m}{\mathrm{m}}^2$. The EIC-PIC assembly is mounted on a printed circuit board (PCB) and connected with wire bonding for electrical I/O for testing and a fiber array for optical I/O for testing. The transmitter (Tx) part of the PIC consists of an array of ring modulators with a $100\mu \mathrm{m}$ pitch. First, experimental characterization of the heater efficiency and thermal crosstalk for the ring modulators is carried out. Those parameters are measured for devices with- and without a substrate undercut (UCUT), which is an additional design feature in which a part of the Si substrate below the device is removed with the intent of improving the heater efficiency.¹⁰ Furthermore, the heater efficiency is measured before and after EIC integration to quantify its thermal impact. The heater efficiency is measured by tracking the ring resonance wavelength shift by applying power to the heater. This results in a figure of merit in units of wavelength per unit power, or nm/mW typically. Next, thermal crosstalk measurements are carried out, quantifying the parasitic heating of a ring modulator from the heaters of the neighboring rings in the array. This is measured by activating the heater in the first channel and measuring the resonance wavelength shift in all neighboring rings.

Fig. 2

Picture of test vehicle: (a), (b) PIC with electrical driver (EIC) hybrid integrated with flip-chip bonding. Cross-section scanning electron microscope (SEM) picture of (c) 3D die stack and (d) sketch: MH and WG. (e) Finite element mesh.

2.2.

Finite Element Thermal Model

A finite element thermal model is made of a PIC with EIC flip-chipped on top. The model is develop using the commercial finite element solver MSC Marc.¹⁴ The finite element model is shown in Fig. 2(e). Using the cross section in Fig. 2(d), the thermal simulation is explained. The simulation input is Joule heat generated in the metal heater (MH; made of tungsten), situated above the waveguide (WG). The total amount of dissipated heat is set to 1 mW, such that the simulation results are normalized per unit of power and can easily be converted to different units. The main point of interest is the resulting WG temperature of the ring modulator, which is extracted from the simulation result as the volumetric average temperature in the Si ring WG. This metric is used to compare the simulation with the measurement result of the heater efficiency. The thermal boundary conditions are natural convection ($h=20\mathrm{W}/{\mathrm{m}}^2\text{-}\mathrm{K}$) on the top-facing surfaces, adiabatic sidewalls, and a thermal resistance ($R_{\mathrm{th}}=8\mathrm{K}/\mathrm{W}$¹⁵) on the bottom face of the PIC, representing the PCB below the die. The material properties used in the simulations are summarized in Table 1. More details on the finite element modeling can be found in Ref. 10. Note that only the EIC-PIC assembly is included in the computational domain; all other parts of the package (Fig. 1) are represented as equivalent boundary conditions.¹⁶ Also, the finite element model is made to mimic the test setup in Fig. 2; consequently, there is no top side cold plate. In Fig. 2(c), a cross section of the interface layer ($\mu \mathrm{bumps}$) is shown. This is a relatively complex layer, with in-plane anisotropy and cross-plane thermal conductivity that depends on the used underfill and metallic composition of the bumps. Two different ways of modeling this layer are compared. First, the actual geometry of the bumps is used in the model (i.e., geometric model). In Fig. 3, the ring modulator is shown along with an array of $12\mu \mathrm{bumps}$ around the device. We opt for including only $12\mu \mathrm{bumps}$ because the neighboring $\mu \mathrm{bumps}$ have the largest impact on the ring modulator. In the actual test chip, the PIC-EIC interface is fully filled with $\mu \mathrm{bumps}$ ($1.5\times 1\mathrm{m}{\mathrm{m}}^2$ area). Including the actual geometry of the $\mu \mathrm{bumps}$ will yield the most accurate results, but it is quite inefficient because of the large mesh size and hence increased central processing unit (CPU) time for simulation. The second method of modeling the $\mu \mathrm{bump}$ layer is by replacing it with an equivalent material with properties that match the combination of $\mu \mathrm{bumps}$ and underfill. To achieve this, the symmetry of the layer is exploited, and a separate, quarter-slice model of the bump is made (Fig. 3). With this highly simplified model, the effective in-plane and cross-plane thermal conductivity can be estimated.¹⁷ Finally, these equivalent material properties are used in the full $\mu \mathrm{bump}$ layer (i.e., equivalent model). The equivalent out-of-plane thermal conductivity of the $\mu \mathrm{bump}$ layer is calculated using the simulated temperature drop across the $\mu \mathrm{bump}$ $\mathrm{\Delta }T=T_1-T_2$ (Fig. 3), given as

Table 1

Thermal conductivity values for thermal simulations,10 UF = underfill in μbump layer.

Fig. 3

$\mu \mathrm{bumps}$ modeling: individual geometric or with equivalent material properties through unit cell approach. The equivalent out-of-plane thermal conductivity is calculated using the temperature drop across the $\mu \mathrm{bump}$ $\mathrm{\Delta }T=T_1-T_2$.

3.1.

Heater Efficiency

The heater efficiency of the ring modulators is measured for four different cases: with and without UCUT and with and without EIC flip-chipped on top of the PIC. The measurement results are shown in Fig. 4. The addition of UCUT in the design increases the heater efficiency, as reported in Ref. 10. Furthermore, the impact of the EIC on the heater efficiency is also significant: for the case with UCUT, a decrease by 44% is observed. The experimental results are summarized in Table 2 and compared with simulation results, which are further discussed in Sec. 4.1. Note that the result of the thermal simulations is the average WG temperature (in units of K/mW), which can be converted to a resonance wavelength shift (in units of pm/mW)¹⁰ to compare with the experimental heater efficiency. The conversion can be done using the temperature-dependence of the ring resonance wavelength, given as

Fig. 4

Measurement of the ring modulator heater efficiency.

Table 2

Ring modulator heater efficiency from experiments (pm/mW) and simulations (equivalent model) (K/mW). The value between brackets is obtained by the geometric model.

3.2.

Thermal Crosstalk

In the second experiment, the thermal crosstalk between the ring modulators is analyzed. This is done as follows: in the array of four ring modulators, only the heater of the first device is actuated. The optical transmission spectrum of each device is measured for difference values of heater power in the first device of the array. Due to thermal crosstalk, it is expected that there will be a small shift in the resonance wavelength in the neighbor’s transmission spectra, even though their heater is not actuated. The measurements are conducted on the test setup (Fig. 2) with passive natural convection cooling on the die top side and with the EIC bonded on top of the PIC. In Sec. 4.2, simulations are carried out with and without EIC to quantify its impact on thermal crosstalk. Furthermore, the boundary condition on the top side of the assembly is replaced with an equivalent thermal resistance that models an actively cooled cold plate, which is more representative of a real CPO package (Fig. 1). In Fig. 5, the measured optical transmission spectra of the ring modulators show the increasing applied heater power. The spectra of all four devices are plotted together. The four ring modulators are positioned on the same bus WG; hence, four resonance peaks are visible in each wavelength sweep (e.g., the green profile in Fig. 5). The first ring modulator, which is actuated, exhibits a clear resonance wavelength red-shift. The first, second, and third neighbor resonance wavelengths are indicated. Their wavelength shift is not clearly visible, so an extra inset is added for the first neighbor. For the devices with UCUT [Fig. 5(a)], up to 26 mW of heater power is applied, which corresponds to a maximum resonance wavelength shift of 8.112 nm, given a heater efficiency of 312 pm/mW (see Table 2). For the devices without UCUT [Fig. 5(b)], these numbers are104 mW of heater power and 17.16 nm resonance wavelength shift, respectively. Because the devices without UCUT are expected to have a heater efficiency, which is approximately half compared with the devices with UCUT, it is important to increase the heater power for devices without UCUT for crosstalk characterization. By doing so, it is ensured that a sufficient resonance wavelength shift is obtained. Because the thermal crosstalk is in the 1% order of magnitude, the measured shift in resonance wavelength from the different neighbors can be estimated as $\mathrm{\Delta }{\lambda }_{\mathrm{neighbor}}(26\mathrm{mW})=8.112\mathrm{nm}$ $\times 0.01=0.08112\mathrm{nm}$. This is a small value compared with the width of the resonance peak of the ring modulator; consequently, it is important to apply sufficient power to the heater. Otherwise, the crosstalk could fall below the measurement precision of the setup. Based on this wavelength shift, thermal coupling is defined as

Fig. 5

Thermal crosstalk measurement with UCUT (a) and without UCUT (b). Both results are with EIC integration. Note that the ring modulators with UCUT (a) are designed for O-band operation and without UCUT (b) for C-band operation.

Table 3

Thermal crosstalk experiment and simulation (equivalent model) of EIC-PIC assembly, in percentages.

4.1.

Heater Efficiency

4.1.1.

Equivalent versus real geometry approach

The first part of the simulation results is the comparison between the equivalent model for the $\mu \mathrm{bumps}$ and the geometric model. In Fig. 6, a temperature contour plot of the ring modulator is shown. The reference case is the cross section of the bare PIC, without EIC [Fig. 6(b)]. There is a clear horizontal temperature gradient as the heat is forced to flow around the UCUT before it can leak into the Si substrate below. When the EIC is added, the temperature contour changes. In Fig. 6(c), the simulation result is shown for the equivalent model. The $\mu \mathrm{bump}$ layer, consisting of the $\mu \mathrm{bumps}$ and underfill, is replaced by material with an equivalent thermal conductivity, calculated with the unit cell model (Fig. 3). In Fig. 6(d), the result is shown for the geometric model. In this case, the actual $\mu \mathrm{bumps}$ geometry is modeled. The local temperature field above the UCUT is different than the equivalent model. However, the main point of interest is the WG: the average WG temperature determines the heater efficiency. In Fig. 7(a), a horizontal, linear temperature profile through the WG is shown for the two model types (geometric and equivalent). In Fig. 7(b), a circular temperature profile along the ring circumference is shown. From this, it can be concluded that, for the purpose of simulating the WG temperature, both the equivalent and geometric models produce similar results.

Fig. 6

Simulation result: (a) temperature contour plot of ring modulator cross section, (b) without EIC and (c), (d) with EIC integration.

Fig. 7

(a) Linear temperature profile through WG and (b) circular temperature profile along the WG circumference.

4.1.2.

Model validation

The heater efficiency simulated with the equivalent model, that is, the average WG temperature, is now compared with the experimental results in Fig. 8. The experimentally observed drop in heater efficiency due to the flip-chip integration of the EIC (42.4% with UCUT and 20.6% without UCUT) is well captured in the model. The cause of this drop can be retrieved from the temperature contour plots in Fig. 6: the flip-chip bonded EIC acts as a heat spreader for the local heat generation in the heater of the ring modulator (RM). In the reference case without EIC [Fig. 6(b)], the heat transfer is forced horizontally by the presence of the UCUT below the RM. If EIC is flip-chipped on top, heat spreading occurs in the EIC, lowering the overall heater efficiency. By the addition of UCUT, the heat flow is forced horizontally through the ${\mathrm{SiO}}_2$ surrounding the device. However, if the EIC is added, a secondary parallel heat transfer path is created, lowering the overall thermal resistance and partially offsetting the efficiency gain by UCUT.

Fig. 8

Measured versus simulated heater efficiency for four cases: with and without UCUT/EIC. Red and orange impact on the heater efficiency with EIC and UCUT is obtained by a thermal modeling study (Sec. 5).

4.2.

Thermal Crosstalk

Section 4.2 discusses the effect of 3D hybrid integration on thermal crosstalk between the different ring modulators. In Sec. 3.2, the experimental results were shown (Fig. 5 and Table 3). In our setup, the thermal crosstalk was measured at three different distances from the heated ring modulator: 100, 200, and $300\mu \mathrm{m}$. At these locations, the relative thermal crosstalk is extracted and compared with the simulation results in Fig. 9, with and without UCUT. The simulation result is extracted in a way which is similar to the method that was used for the experimental coupling coefficients in Eq. (3): the coupling is defined as the temperature $T(x)$ at distance $x$ relative to the temperature in the heated WG $T_{\mathrm{ref}}$, in the PIC WG plane: $C(x)=T(x)/T_{\mathrm{ref}}·100\%$. The first conclusion from the simulations is that the addition of UCUT lowers the thermal crosstalk, which is also observed experimentally. This is mainly caused by the higher reference temperature $T_{\mathrm{ref}}$, that is, the higher WG temperature of the heated ring modulator. The UCUT itself has little impact on the absolute temperature at a large distance from the heated device.¹⁸ Also, for large distances ($>200\mu \mathrm{m}$), the thermal crosstalk is quasi-constant, similar to the results reported in Ref. 19. To assess the impact of the flip-chip EIC integration on the PIC, the calibrated FE model is simulated with and without EIC [Fig. 9(b)] for the case with UCUT. The addition of the EIC increases the thermal crosstalk by 44.4%. Based on the previous conclusions about the heat spreading in the EIC, this result is expected. The flip-chip integration of the EIC causes additional lateral heat transfer, which in turn enhances thermal crosstalk in the PIC.

Fig. 9

(a) Thermal crosstalk measurement and simulation result with EIC. (b) Simulated crosstalk with and without EIC.

All reported crosstalk values are for the case without an active cooling solution on the EIC-PIC assembly top side. This allows a direct comparison with the experiments (Fig. 2). However, a more realistic thermal packaging approach for CPO-based transceivers is based on liquid cooling as shown schematically in Fig. 1(a). This scenario can be simulated by adapting the thermal boundary condition on the EIC top side by replacing the natural convection boundary condition with a thermal resistance of 0.1 K/W. The simulation results are shown in Fig. 10. The reference case corresponds to the device with UCUT and EIC flip-chipped on top, with natural convection cooling. The thermal crosstalk for the reference case and the top side cooling case is plotted in Fig. 10(a), and there appears to be no difference between both. However, in Fig. 10(b), the same data are shown, but zoomed-in around 1%. Here, the impact of the top side cooling is clear. The long range thermal crosstalk is greatly reduced (49.9%). This result shows a pathway for minimizing the effects of thermal crosstalk in heater-based PIC architectures. Furthermore, the impact of the top side cooling on the heater efficiency is negligible ($-0.56\%$).

Fig. 10

(a), (b) Simulated thermal crosstalk for the reference case (test setup) and for a real package case (top-side cold plate).

5.1.

Underfill

To maximize the interface thermal resistance, there are two degrees of freedom that can be changed: the metallic connections and the underfill. The impact of a low thermal conductivity underfill on the overall effective thermal conductivity can be simulated with the equivalent $\mu \mathrm{bump}$ model. The result is shown in Fig. 12. The reference underfill thermal conductivity is $k_{\mathrm{UF}}=0.18\mathrm{W}/\mathrm{m}\text{-}\mathrm{K}$,²¹ a standard value for an unfilled epoxy underfill. A simulation with $k_{\mathrm{UF}}=0\mathrm{W}/\mathrm{m}\text{-}\mathrm{K}$ results in a decrease of the effective thermal conductivity from 9.38 to 9.22 W/m-K. This indicates that the effective thermal conductivity of the underfill-$\mu \mathrm{bump}$ array is insensitive to the type of underfill used in dense $\mu \mathrm{bump}$ arrays. In other words, the thermal conduction path between EIC-PIC is dominated by the metallic connections that have a high thermal conductivity.

Fig. 12

Effective thermal conductivity of the $\mu \mathrm{bump}$ layer as a function of the underfill thermal conductivity.

5.2.

Metallic Connections: Cu Lines and μBumps

Two aspects of the metallic connections are investigated by means of a thermal modeling study: (1) the metallic linewidth of the connections to the $\mu \mathrm{bumps}$ in the PIC and (2) the local $\mu \mathrm{bump}$ size and placement around the ring modulator. First, the linewidth is varied in the Cu connections in the M2 BEOL layer from the ring modulator to the $\mu \mathrm{bumps}$. The reference linewidth is $2.4\mu \mathrm{m}$, which is decreased down to $0.4\mu \mathrm{m}$ in the model. The impact on the heater efficiency is plotted in Fig. 14. Up to 30.1% heater efficiency gain is possible for the smallest linewidth. Changing the Cu linewidth obviously impacts the electrical performance of the ring modulator. Mainly, the parasitic resistance between the device and its driver will increase. The impact on the 3 dB bandwidth can be estimated using literature data on equivalent circuit parameters. The interconnect resistance ($\sim 1\mathrm{\Omega }$²²) is typically much smaller compared with the series resistance of the WG pn-junction (200^23,24 to 350²² $\mathrm{\Omega }$). The electro-optic time constant is $\tau =\mathrm{RC}$, and the 3 dB bandwidth is $f_{3\mathrm{dB}}=1/(2\pi \tau )$, which results in a 1.6% to 2.9% drop in electro-optic bandwidth for a six times higher interconnect resistance in the case of the smallest Cu linewidth. Also, decreasing the Cu linewidth poses a concern for reliability, more specifically electromigration failure.²⁵ A smaller cross-section results in larger current density. The peak current during the charging of the WG capacitance can be estimated with $I=V/R·e^{-t/\mathrm{RC}}$. Assuming a $-2\mathrm{V}$ ring modulator bias, the peak current amplitude is $\sim 5.5\mathrm{mA}$, which is much lower to the expected current for the heater connections of the device ($\sim 30\mathrm{mA}$) for full free spectral range tuning; furthermore, this peak current is only maintained very briefly and is not constant in time. This all points to the fact that the radio frequency (RF)-connections of the ring modulator are more robust against electromigration failure compared with the heater connections.

Second, the impact of adapting the $\mu \mathrm{bump}$ design is simulated. Two design parameters are varied: the $\mu \mathrm{bump}$ size and placement around the ring modulator. The $\mu \mathrm{bump}$ size is reduced by 50%, and the simulation result is shown in Figs. 13(a) and 13(b). Reducing the size results in two thermal effects: first, the thermal resistance increases because of the lower metallic volume fraction in the $\mu \mathrm{bump}$ layer (desirable effect). Second, if the $\mu \mathrm{bump}$ pitch is kept constant, a smaller $\mu \mathrm{bump}$ results in a larger spacing between the ring modulator and $\mu \mathrm{bump}$, which limits unwanted horizontal heat spreading. These effects combined result in a $+12.1\%$ heater efficiency (Fig. 14). Now, we explore further the effect of increasing the spacing between the $\mu \mathrm{bump}$ and ring modulator. The reference $\mu \mathrm{bump}$ size is kept and the spacing of the two closest $\mu \mathrm{bumps}$ is increased. In Fig. 15, this concept is shown. This results in an irregular $\mu \mathrm{bump}$ pattern, which introduces additional integration challenges such as the loss of periodicity in the array, which are not discussed further. In Fig. 15, the heat flux through the $\mu \mathrm{bumps}$ is shown for the reference case and for the case with $20\mu \mathrm{m}$ additional spacing between the ring modulator and $\mu \mathrm{bumps}$. For the second case, a significant decrease in $\mu \mathrm{bump}$ heat flux is observed because the local heat sinking effect is decreased. This effect is further illustrated in Fig. 13, where a cross section of the model is shown with temperature contours. In Fig. 13(a), the reference design is shown. In Fig. 13(c), the design with added $\mu \mathrm{bump}$ spacing is shown. The effect on the heater efficiency in function of $\mu \mathrm{bump}$ spacing is plotted in Fig. 14. Moving the $\mu \mathrm{bumps}$ away from the device increases the heater efficiency up to 18.6%. After a spacing of $\sim 20\mu \mathrm{m}$ between the edge of the RM and the $\mu \mathrm{bump}$, there are diminishing returns for further spacing increases.

Fig. 13

Cross section of ring modulator and $\mu \mathrm{bumps}$, with simulated and normalized temperature contours. (a) the reference design, (b) the adapted design with $-50\%$ $\mu \mathrm{bump}$ size, and (c) the increased gap between ring modulator and $\mu \mathrm{bumps}$.

Fig. 14

Simulation result: (a) the heater efficiency as a function of the gap between the ring modulator and $\mu \mathrm{bump}$. The green data point is obtained for $-50\%$ size $\mu \mathrm{bumps}$ at the original pitch ($50\mu \mathrm{m}$); see Fig. 13(b). Decreasing $\mu \mathrm{bump}$ size effectively increases the $\mu \mathrm{bump}$-RM gap. (b) The heater efficiency as a function of the Cu linewidth.

Fig. 15

(a) Model showing the ring modulator and $4\times 3$ array of $\mu \mathrm{bumps}$ in its close vicinity and increased gap between the ring modulator and its $\mu \mathrm{bumps}$. (b) Top view of the heat flux through $\mu \mathrm{bumps}$ for the reference case and moved $\mu \mathrm{bumps}$ case.

Furthermore, changing the material composition of the $\mu \mathrm{bumps}$ or the EIC itself could also be done for further thermal improvements, but this is left for follow-up research. In conclusion regarding the thermal improvements, in combining smaller $\mu \mathrm{bumps}$ with larger spacing between the RM and $\mu \mathrm{bumps}$ together with decreased Cu linewidth, an overall heater efficiency gain of 49.2% is obtained. This improvement is relative to the reference case with EIC bonded on top of the PIC. In absolute terms, the heater efficiency is increased from 3.08 to 4.60 K/mW (Fig. 8), which indicates that the thermal penalty on the heater efficiency due to the EIC stacking is reduced from 43% to 20% though the proposed mitigation solutions. The efficiency loss due to heat spreading in the EIC can be offset partially, but not fully. For further improvements, more drastic design changes, such as increased UCUT area, are required.