As semiconductor manufacturing migrates to more advanced technology nodes, the performance improvement anticipated from scaling has failed to match expectations. This failure is due to the emergence of layout-dependent effects (LDEs) not encountered in the design flow prior 65nm process node. We propose a novel methodology that allows the early detection of LDEs during schematic creation. Different from all previous works, this methodology accurately calculates LDEs by interfacing interactively with a simulator tool. Our research indicates that no previous works suggested the use of “on-the-fly” simulation, using Eldo Interactive, to study LDEs. In fact, the use of Calibre tools  has been suggested to help the designer check certain basic electrical constraints (like matching) under the existence of LDEs, by specifying the matching condition as a comment added to the original Pyxis schematic netlist.  These comments are then transformed into verification rules that are added and checked by Calibre. The proposed flow is tested on a 40nm OTA design, with results not only as accurate as those previously obtained from post-layout analysis, but also equal to or better speed of execution, demonstrating the practicality of using “on-the-fly” simulation to detect and resolve LDEs early in the design flow.