We demonstrate a manufacturing approach of nanostructures on the large surface area of GaN-based LED chip to
improve the light extraction efficiency. We prepared the nanoporous anodic aluminum oxide (AAO) template on an
aluminum foil by the conventional two-step anodization. Using the AAO template as etching mask, we successfully
transferred the nanoporous structures to the surfaces of GaN-based LEDs by inductively coupled plasma dry etching.
About a quarter of two-inch GaN-based LED chip was patterned by the nanostructures. The pore spacing was modulated
from 100 nm to 400 nm. The improvement of light extraction efficiency of the device was achieved. A light output
power enhancement of 42% was obtained from the p-side surface nanopatterned LEDs compared to the conventional
LEDs on the same wafer at 20 mA. This approach offers a potential technique of nanostructures fabrication on GaNbased
LEDs with the advantages of large area, rapid process and low cost.
Controlling fabrication of mono-dispersed and well-aligned arrays of one-dimensional (1D) nanostructures, nanowires or nanotubes, will benefit a lot for the investigation of their physical properties and their potential use in nanolasers, chemical and biological sensors, and nanoelectrode arrays for solar energy conversion and catalysis. In our previous works, we have fabricated a broad range of semiconductor nanowire arrays by electrochemical synthesis in template. In this present, we design a well-controlled process to fabricate uniform nanotube arrays through a multi-step template replication and electrodeposition approach. The resulting nanotubes with uniform wall thickness and diameters along the entire tubes are highly ordered and mono-dispersed. Moreover, we develop a supercritical drying route to avoid the clustering or collapse of the nanowire arrays caused by capillary force during the removing of the template. By this strategy, we have obtained large-scale, non-collapse, well-aligned nanowire arrays on conductive substrates. Final, the uses of these nanowire arrays for future nanodevices are discussed.