In semiconductor manufacturing, the selective removal of the carbon mask after etching has become increasingly challenging with the introduction of Gate-All-Around (GAA) technologies. This transition has brought greater procedural complexity, necessitating more process steps to accommodate intricate and vertically structured designs. Consequently, there arises a need to reassess the appropriateness of traditional methods. Traditionally, the process relied on high RF power plasma to eliminate the carbon mask, resulting in the generation of large quantities of ions that could potentially compromise the integrity of thin film materials. As materials refine and designs require increased vertical scaling, associated risk factors are accentuated. Over-cleaning leads to ion damage, exemplifying the limitations in enhancing device performance. To overcome these challenges, an innovative selective mask removal (SMR) technology has been developed using Metastable Activated Radical Source (MARS). Utilizing MARS, radicals derived from hydrogen or oxygen exhibit lower energy levels, minimizing material damage on the wafer surface during the SMR process. This revolutionary technique significantly reduces the thickness of native oxide layers after SMR, lessening electrical resistance in critical processing steps and enhancing device performance. Furthermore, it enables improved surface passivation strategies, preventing the formation of native oxide and enabling multivalent passivation. These advancements mark a significant step in reducing pattern-induced damage in the GAA era, aligning with sustained progression in line with Moore's Law.
Semiconductor process development for state-of-the-art devices is a complex task that requires up to years of development. The complexity comes from the need to tune a significant number of process knobs in latest process tools, to meet multiple on-wafer performance targets, across an entire wafer. AppliedPRO® is a software and library of algorithms developed by Applied Materials for process recipe optimization to meet simultaneous process requirements across the entire wafer. The software is tailored to semiconductor use-cases and designed to be primarily used by process engineers to make critical decisions with confidence during process development. Over 100 use-cases have been generated for various semiconductor chips manufacturers, showing faster development time, less development resources, and higher process engineer productivity. This paper shows the use-case of Samsung N+1 Logic BEOL Spacer-Etch process recipe optimization using AppliedPRO®. We utilized AppliedPRO® structured design of experiment methodology and machine-learning algorithms to simultaneously model 10 process-recipe knobs of Applied Materials’ Centris® Sym3® X Etch system and their effect on 8 on-wafer metrics, and determine optimal process knob conditions for minimizing Spacer-tail, which is a key performance metric, while keeping other metrics close to spec. These optimized conditions reduced Spacer-tail by 73% on coupons, which was also validated on full-wafer. These optimal results were previously unachievable in all the previous experimental trials before introducing AppliedPRO®.
As device scale down to sub 3nm, NMOS/PMOS boundary patterning becomes critical in logic product. This patterning requires highly directional etching while maintaining high selectivity to the base metal layer. In this paper, we demonstrated that the ion energy has the trade-off between the profile verticality and the surface damage. The ion energy was strongly controlled by the bias voltage and surface damage was improved with lower bias voltage, but profile verticality was deteriorated because of the ion angle dispersion. To enhance the profile verticality the carbon rich gas was added as the top passivation. The proposed method will be a practical in sub-3nm logic boundary patterning.
Patterning cost and complexity continues to rise with every node. Although EUV lithography has extended dimensional scaling, its limitations have required the industry to implement multi-EUV and other complex patterning schemes. Single exposure EUV patterning is limited by stochastic defects at sub-36nm pitch. Also, counter-scaling between pitch and tip-to-tip spacing limits how close patterned features can be packed in the non-preferred direction. Multi-EUV patterning schemes significantly increase cost while also introducing Edge Placement Errors (EPE). We discuss here an innovative pattern shaping capability which can elongate pre-defined line/space and hole patterns to address these challenges. We will discuss various process knobs including reactive chemistry and material selectivity which can be tuned to allow precision pattern shaping. We will also show how this capability can be used for sidewall processing for applications such as asymmetric spacer removal. Directional pattern shaping has the potential to be a powerful tool in the patterning engineer’s toolbox to help further extend Moore’s law.
Conference Committee Involvement (7)
Advanced Etch Technology and Process Integration for Nanopatterning XIV
23 February 2025 | San Jose, California, United States
Advanced Etch Technology and Process Integration for Nanopatterning XIII
26 February 2024 | San Jose, California, United States
Advanced Etch Technology and Process Integration for Nanopatterning XII
28 February 2023 | San Jose, California, United States
Advanced Etch Technology and Process Integration for Nanopatterning XI
26 April 2022 | San Jose, California, United States
Advanced Etch Technology and Process Integration for Nanopatterning X
22 February 2021 | Online Only, California, United States
Advanced Etch Technology for Nanopatterning IX
25 February 2020 | San Jose, California, United States
Advanced Etch Technology for Nanopatterning VIII
25 February 2019 | San Jose, California, United States
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