This paper presents adder circuits of various architectures aimed at reducing static power dissipation. Circuit
topologies for basic building blocks were evaluated for fabrication technologies of 65nm down to 32nm, and
simulation results are presented. This work has lead to the development of various low power adder circuits and
provides comparative analysis leading to the recommendation that a variable size block carry select adder is the
best performer, taking into consideration both static and dynamic power dissipation.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.