The optical sensor signal processing requirements for ballistic missile defense are reviewed. The paper emphasizes the signal processing techniques employed, their requirements, and the resultant impact on signal processor hardware. Highlights of the system and sensor are included for understanding. Signal Processing requirements are addressed for both the exo and endo optical sensor systems. The paper constitutes a review, delineating the ten to hundred million instructions/sec throughputs, the several million bytes of storage, the advanced real-time algorithm developments required, and the requirements on signal processing architecture and hardware.

This paper comprises a description of Synthetic Aperture Radar (SAR) processing approaches and a discussion on the processor complexity measures. The objective of the paper is to provide basic system knowledge on the design of a real-time signal processor for spaceborne synthetic aperture radar. A review of SAR sensor performance capability and general electronic processing approaches will be given first. The discussion of SAR processor complexity is divided into two areas: the arithmetic complexity and the control complexity. A generalized treatment of these subjects is provided. The results could be readily extended to special cases.

This paper presents a description and some preliminary results of a modular, flexible signal processor bread-board which is used to evaluate the practical performance of spatial and temporal algorithms to reduce background clutter for onboard surveillance applications where data compression is mandatory. At present, the breadboard treats the target detection process by implementing several temporal and spatial filters which operate on both real sensor data and pseudoscenes. The S3P processes frames of mosaic sensor data with 32x32, 64x64, and 128x128 pixels at frame rates up to 100 fps. The operations performed in S 3P with hardware and an Intel 8086 micropro-cessor include (1) preprocessing; (2) frame registration and interpolation; (3) classical first-, second-, and third-order differencing; (4) nonrecursive temporal filter with updated optimal statistical coefficients; (5) band-pass recursive temporal filters; and (6) 3x3 spatial filter using an optimal set of coefficients chosen to minimize the mean-square noise. The breadboard achieves its flexibility through modularity and a bus /pipeline architecture and, hence, serves as a testbed for new algorithms. Preliminary results for the nonrecursive temporal filter will be presented for selected input scenes. It is seen that accuracy and arithmetic format are important in achieving good performance.

Some initial considerations are given for an Earth-orbiting relay system using optical data links from deep space and RF links to ground. The advantages of such a system are presented, and some preliminary design concepts and modulation formats are proposed. The tracking and pointing problem is discussed with some indication of capabilities and limitations.

When using an adaptive filter for real-time signal processing, the filter coefficients must be modified in real time and fast computation methods for determining optimal filter coefficients are essential. The optimal coefficients for signal detection and background suppression depend upon the statistics of the background noise and the characteristics of the signal pulse. A novel approach for calculating optimal filter coefficients has been devised which makes use of symmetries in the coefficients (derived from symmetries in the noise statistics and the signal) to reduce computation requirements significantly. For example, with a five-by-five two-dimensional spatial filter there are 25 coefficients which must be determined, and the conventional approach requires over 5000 multiplications and 5000 additions. When symmetries exist, there are only 6 distinct values for the 25 coefficients, which reduces the required calculations to 75 multiplications and 75 additions. Detailed examples of temporal filtering, spatial filtering, and multispectral filtering illustrate the efficacy of the procedure in practical situations.

Images of objects and scenes on earth taken from high and low altitude aircraft have been used for many purposes including natural resource analysis, weather prediction and navigational aid. For an image of low contrast, the amplitude variations of the high frequency components of the video are small and can be masked by noise introduced during recording and transmission. Analog and digital enhancement techniques are used to enhance and retain the detail information of the scene represented by the high frequency components. Experimental results are presented for the processing of optical and radar images.

Based on digitized TV frames a computer simulation study was conducted on a motion-adaptive TV data compression scheme, defined as one in which a 2-dimensional transform applied to subblocks is followed by the transmission to the receiving site of only changed subblocks. Performance was measured both by calculation of Normalized Mean Square Error and by subjective viewing of reconstructed frames. Two systems designs leading to 512x512 resolution operation (one based on the Hadamard and one on the Discrete Cosine Transform) were prepared.

Visual system resolution is the first important criterion mentioned in a functional specification for the real time dynamic simulation of any visual system. This criterion has a profound effect on the estimation of the cost and the complexity of any dynamic visual system design of very wide field of view. What is essential in terms of static and dynamic resolution of the simulated visual system for proper pilot training in tactical combat missions is described in this paper, around a spectrum of highly relevant conjectures such as the physical limit of computer processing, innovations in digital image processing, and the speed of perception in visual information processing by the human brain.

Video images received by a High-Energy Real-Time Inspection System (HERTIS) developed in this laboratory were processed using frame integration, image subtraction, spatial averaging, and histogram analysis. This system demonstrated a sensitivity of 2%-1T through a 4" simulated propellant sample in an automatic inspection process.

Based on the systolic array approach, new designs of special-purpose devices for filtering, correlation, convolution, and discrete Fourier transform are proposed and discussed. It is argued that because of high degrees of simplicity, regularity and concurrency inherent to these designs, their VLSI implementation will be cost effective.

The use of automated and semi-automated drilling systems for fastener holes in aircraft manufacturing has created the need for a rapid, low-cost technique for monitoring these drilling operations. In the case of automated drilling, inspectors would be required to monitor and inspect millions of drilled holes each year. To reduce the need for visual inspection, an on-line, real-time image processing system is proposed. Image pattern recognition techniques applicable to hardware implementation have been applied to video images of interior surfaces of drilled holes. Classification results are presented, along with an approach for automated quantitative "accept/question/reject" decisions. A functional hardware implementation of the processor is described.

Basic devices required for analog microwave signal processing have been demonstrated using magnetostatic wave propagation in epitaxial yttrium iron garnet films. 100 nsec delay lines with bandwidths of 400 MHz, dispersive delay lines with differential delays of 200 nsec and bandwidths of 1 GHz and a programmable tapped delay line, all operating at S-band through X-band, are described. The operation of a new type of device, a signal-to-noise enhancer or power expander, is discussed which has the opposite characteristic to the more familiar microwave limiter. All these devices share the unique features of operation directly at microwave frequencies and frequency tunability via the strength of the magnetic bias field which is required for their operation.

Real time optical computing of the two dimensional ambiguity function based on the use of one dimensional Bragg cells as input transducers and the use of unique coherent optical systems as the computing architectures will be presented. Two techniques using optical spatial integration have been invented and demonstrated to be suitable for ambiguity processing. Their key feature lies in the utilization of optics to transform the two one dimensional spatial functions into the associated two dimensional ambiguity function.

This paper contains the results of a joint investigation by the US Army Engineer Topographic Laboratories (ETL) and the US Army Tank-Automotive Research and Development Command (TARADCOM). The main emphasis is to describe investigations using Direct Electronic Fourier Transform (DEFT) technology and the DEFT method to generate Fourier transforms for surveillance and countersurveillance. These investigations include quantitative results which are obtained with an early device and a comparison of these results with subjective human judgments. A computer simulation of DEFT spectra is performed for the purpose of bandwith ex-tension and signal-to-noise improvement. DEFT devices are a recent advance in acousto-optic technology. Early devices generate a real-time, one-dimensional Fourier transform of a two-dimensional image. This Fourier transform is a limited bandwidth radio frequency spectrum representing the image. This paper contains a very brief description of DEFT technology and appropriate references on the development of the DEFT device.

This paper presents the experimental results (i.e., spectra) obtained with a Direct Electronic Fourier Transform (DEFT) device. Emphasis is placed on the use of DEFT spectra for terrain feature classification. These spectra indicate the potential of DEFT technology for distinguishing between natural features and cultural or man-made features. These same spectra appear to have potential for distinguishing between certain subclasses of terrain features, e.g., open fields, bodies of water,and woods. A potential application of DEFT spectra could be the preliminary analysis of aerial imagery to automatically flag certain photographs for subsquent detailed analysis by a human photointerpreter (PI), and to automatically select or reject specific photographs before digitization for mapping or other purposes. New devices use surface acoustic waves (SAW) to generate a two-dimensional limited bandwidth Fourier transform of an image in real time without the aid of a computer. These devices permit spectra analysis for a two-dimensional image as a communications engineer would analyze the RF spectrum of a radio signal. Appropriate references and a brief description of DEFT technology will be presented for those unfamiliar with this advance in solid state, acousto-optic technology.

This paper analyzes the device characteristics of acousto-optic Bragg cells for signal processing applications. Design parameters of efficiency, bandwidth, resolution and sidelobes, and distortion are considered. Phase distortion is of particular importance in imaging type acousto-optic signal processors such as correlators and convolvers. Techniques for optimizing these performance factors are discussed.

This paper is concerned with the anplication of ontics to digital comnutina. We use a Huahes Liquid Crystal Liaht Valve (LCLV) as an active ontical element where a weak light beam can he used to control a strona liaht beam with either a Positive or negative gain characteristic. With this device as the central element we have demonstrated the ability to produce all the binary logic gates and to produce bistable states (flin-floos) which can themselves he used as logic gates or as memory elements. The aates and flip-flons have been used in the desian of ontical equivalents to a few simple sequential circuits such as shift registers and accumulators. These circuits then have tvnical annlication as a binary ontical integrator. The desians will he discussed and exneriments showing the limitations of the LCLV for this work will he presented. A brief discussion of coding theory as annlied to ontical computing will also be given.

An optical processor which performs binary arithmetic operations can combine the parallel processing capacity of optical systems with the accuracy and programmability inherent to digital processors.) Such a Digital Optical Processor (DOP) will be useful in many image processing applications as well as in solving problems which are two-dimensional in nature. A DOP must first convert the analog images into binary images via an optical A/D converter and then process these binary images through an Optical Logic Unit (OLU). The DOP must also contain optical memory devices to store intermediate results of computation and a control unit to direct the operation of all the components mentioned above. Complex digital operations can be achieved by using the OLU and optical memory repeatedly under the direction of the control unit. One such structure which requires a minimum of hardware is shown in Figure 1. In this paper we will summarize briefly the worK done at UCSD on all these components of a DOP.

Attention is given to various methods by which the accuracy achieveable and the dynamic range requirements of an optical computer can be enhanced. A new time position coding acousto-optic technique for optical residue arithmetic processing is presented and experimental demonstration is included. Major attention is given to the implementation of a correlator operating on digital or decimal encoded signals. Using a convolution description of multiplication, we realize such a correlator by optical convolution in one dimension and optical correlation in the other dimension of a optical system. A coherent matched spatial filter system operating on digital encoded signals, a noncoherent processor operating on complex-valued digital-encoded data, and a real-time multi-channel acousto-optic system for such operations are described and experimental verifications are included.

A time-integrating optical correlator has been devised in which a digital shift register-LED array combination provides the delay-and-multiply operation usually performed by an acousto-optic cell. The optical subsystem is extremely compact and should be able to operate at bandwidths from D. C. to 100MHz. Delay time range and resolution can be varied over a wide range simply by changing the frequency of the clock driving the shift register.

Because of the rapid advances in multiplication hardware, the most time consuming processing step in Fourier Transform will be the number of memory accesses rather than the number of multiplications. An algorithm of Continuous Fourier Transform (CFT) which minimizes memory access was developed. It can be implemented with existing technology and is potentially faster than FFT, particularly for processing continuous, real-time signals.

This paper summarizes a survey of concurrent-processing computer systems, particularly their descriptive differences and performance. The motivation is the high data processing rates required by ever-larger applications of infrared sensors and radar for data accumula-tion and the speed constraints of technology. The scope of the application and the technological limitations have caused consideration of alternative computer systems architectures for signal processing. In support of this, a survey was done of installations which are built and functioning, first to assess the architecture's application to signal processing, and second, to understand the difficulties inherent in developing an operational concurrent-processing computer system. The surveyed systems include C.mmp, Cm*, PLURIBUS, S-1, ILLIAC IV, STARAN, PEPE, CDC *100, TIASC, CRI - CR1, and the fault tolerant systems JPL-STAR and SRI-Sift. Some systems have been excluded from this paper because they either are not completed to an operational stage or are classified. In this investigation of system architectural issues for signal processing applications, it became evident that no effective systems characterizations for concurrent processors exist. Furthermore, performance measures for these systems are awkward and poorly related to the characterizations. The performance mea-sures thus need refinement. A descriptor is proposed which contains the elements of data flow, control and reliability and to which the performance measures can be properly related.

Military radar systems require complex and adaptive signal processing to achieve optimum performance. In addition to this performance requirement is the need for high system reliability. A signal processing architecture that is modular and programmable has been a critical requirement for many years. The approach used to meet this requirement necessitates the use of identical VLSI/VHSIC components. The task of evaluating a design is normally accomplished by breadboarding. However, this can not be done until the IC's have been developed. An obvious alternative is to simulate the system at the register-transfer and or gate level. This method has been used in the past but is limited to system fragments due to the excessive storage and CPU time required. In order to validate advanced radar signal processor hardware, software, and firmware, a digital simulation tool has been developed which allows the system designer to evaluate alternatives with minimum effort, storage, and execution time. The top-down design procedure is utilized to guide the user from system requirements to final system design.

A contractual study of Advanced On-Board Satellite Signal Processor technology (DARPA, USAF-RADC Contract F30602.78.C.0028) included, in part, evaluation of various processor architectures and integrated circuit components for use with military sensor systems, especially electro-optical and radar, for the era of the late 1980's. High level architectural tradeoff studies were performed in a novel application of the simulation language, ECSS/Simscript. Typical statistical results of the simulation are shown, illustrating how the data are used to measure throughput, to estimate prime power needs to discover contention in array processing, and to provide preliminary guidelines for allocation and proportioning of signal processor resources. Component studies indicated that a programmable high speed signal processor element containing logic, control, and local memory could be realized perhaps on a single VLSI chip. Array architectures evaluated by simulation were capable of satisfying a wide spectrum of mission requirements. Anticipated progress in military and commercial IC technology should provide a basic pro-cessing element adequate for all needs. The switching and management of data flow to and from bulk memory, which appears to be a very difficult software analysis problem, can be eased by guidelines derived from simulation.

A digital, fault-tolerant signal processor, (FTSP) has been developed to address the needs of minimally attended radar systems. The design emphasizes fault-tolerant aspects in both hardware and software and is based on a network of custom-built microprocessors. This paper presents an overview of the FTSP, its fault tolerance philosophy, and an application to a fault-tolerant surveillance radar.

A signal processing application program for a multiple processor system is developed. The suitability of the Ada language in describing signal processing is examined. In particular the areas of multitasking, synchronization and data structures are examined.

An operation common to many applications of high-speed, real-time signal processing is two-dimensional filtering. Recent advances in memory technblogy and residue arithmetic allow high-speed implementation. A two-dimensional five-by-five matrix convolution filter for pulse matching was implemented in residue arithmetic using programmable read only memory (PROM). The simple architecture of this all-PROM filter permits easy pipeline design and the inherent modular structure of residue arithmetic minimized the design overhead. The filter operates at 20 million operations per second with emitter coupled logic (ECL) PROMs. This filter has options such as elementary error detection, multiple patterns matching, and adaptive filtering. An Intel 8086 microprocessor was used as a controller to the filter.

Many current infrared (IR) optical telescope systems require the resolution of closely spaced targets which are optically unresolved. The real-time implementation of a super-resolution algorithm is defined and its performance characterized. The application of this algorithm in a distributed signal processing environment is discussed and its simulation on a distributed computer testbed is outlined.

The S-1 family of uni-and multiprocessors is an extremely high performance but relatively inexpen-sive general purpose set of digital processing systems being developed for the most demanding National security applications. A typical S-1 system consists of from one to sixteen S-1 uniprocessors sharing up to 4 gigawords of uniformly addressed main memory. Each uniprocessor of the current (Mark IIA) generation has computational power roughly equivalent to that of a CRAY-1. In this paper, we give a general description of the S-1 Mark IIA uniprocessor and a somewhat more extensive discussion of its signal processing hardware and hardware-executed algorithms. Our focus is a discussion of the felicitous properties of the uniprocessor components that make the S-1 system a powerful general purpose digital signal processor.

A totally digital approach to radar beam forming implementation is being developed. This paper describes the signal processor design approach, with emphasis on the methodology employed to maximize the payoff of VLSI technology. An emulation of the beam former was developed using a network of microprocessors to allow algorithm development and parameter verification.

The solution of real-time sensor data processing problems with multi-microprocessor architectures of the multiple instruction multiple data stream (MIMD) class is limited by the structure of the interconnection network. A class of real-time sensor processing problems is analyzed to identify required network structures for use in evaluation of candidate interconnection networks. Several fundamental interconnection patterns are identified--macropipeline, K-nearest neighbors, binary search tree, one-n, n-one, one-n with groups of i, and random connection. A general model for a multi-microprocessor testbed is presented, and three candidate interconnection networks--ring, crossbar, and cube--are described for realizing the fundamental structures. Measures are identified for evaluating the candidate networks, and current results of the evaluation are presented.

Systems Control, Inc. has developed an array processing system designed to efficiently process and manipulate large data arrays. The system interfaces to a host computer and consists of an AP-120B array processor, an external bulk memory system and special software. SPRINT was initially developed for the Air Force Avionics Laboratory for processing Synthetic Aperture Radar (SAR) data. In this type of application, the need arises to process large data arrays (up to 5,000*10,000) with reasonable response times. The system uses a simple command language for processing and manipulating large data arrays and the software allows interactive and shared usage of hardware resources.

A novel method for real time track assembly is presented which identifies new tracks, assigns measurements to existing tracks, and eliminates false tracks. The method utilizes a sequence of two-dimensional frames of binary data from an infrared sensor where binary 1 in a picture element indicates target or noise above threshold and binary 0 is below threshold. Successive sets of two-dimensional frames are combined and then screened using a three-by-three pixel window. The track assembly is based upon neighborhood coding and "track scoring" which uses the binary configuration in the three-by-three window to distinguish between target tracks and noise. The method makes use of successive levels of data processing, and in a cluttered environment (noise in 3% of the pixels) it may be necessary to use three or more levels to eliminate false tracks due to noise. A special coding technique is developed for the Floating Point System AP-120B off-the-shelf array processor to allow processing of 160,000 pixels per second independent of the number of targets. This paper explains the coding scheme and the array processor mechanization.

The processing of digitized infrared images in real time requires more processing power than usually provided by a single sequential processor. A system of tightly-coupled 16 bit microcomputers (INTEL 8612) is being developed to provide the needed computational capa-city. This paper first describes an image processing program for detection of moving targets in infrared images. It then describes how several microcomputers on a system bus form a cluster and how a complete star bus switch network permits memory references between clusters. The operating system allocates code and data segments to memory in order to minimize bus contention. Several computational processes are multiprogrammed on each microcomputer. Criteria for partitioning the algorithms into explicit processes and segments is discussed.

An interactive and recursive signal processing system was designed using a top-down approach. The system design is flexible and readily adapts to many types of signals. This is obtained by defining a set of signal processing procedures which permit a rich set of algorithm branches and domains. Recursion paths in the system allow signal enhancement and waterfall displays of intermediate results. Four reentry points into the system provide for interactive or continuous processing. The system has been'implemented with the 16 bit TI 9900 microcomputer and used extensively for both research and instructional purposes. Commonly used signal processing algorithms have been timed and results are presented herein.