2.1

EMCCD (electron multiplying CCD) for space science and astronomy

The CCD311-20 has been developed for use in the Coronagraph in NASA’s Nancy Grace Roman Space Telescope (RST, formerly known as WFIRST). The CCD311-20 is largely based on the CCD301-20 test chip, which itself was a variant of Teledyne e2v’s commercial CCD201-20 sensor. The CCD201-20 is a frame transfer EMCCD with an active imaging area of 1024 x 1024 13μm square pixels, designed for back-side illumination. For the RST CGI the back-surface light shield is removed from what was previously the store section, which allows the bottom half of the pixel array to be used for imaging. The key features of the CCD311-20 are summarized in Table 1 and more information on the sensor development and characterization can be found in Harding et al. [1].

Table 1:

EMCCD CCD311-20 key features.

For the test chip design and characterization test activities, the CCD311 has the following changes from the CCD301 test chip design:

The CCD qualification phase of the program for RST CGI is complete with the production test phase due to start imminently.

Figure 1:

Photo of the EMCCD CCD311-20 in its handling jig.

2.2

CCD for soft X-ray astronomy applications - SMILE

The Solar wind Magnetosphere Ionosphere Link Explorer (SMILE) is a soft X-ray mission observing photon energies of 200 eV to 2000 eV. This mission is a collaboration between ESA and Chinese Academy of Science [2]. For this mission the Teledyne e2v CCD370 has been selected. To minimise the CCD CTI degradation due to proton radiation impact, the focal plane has a temperature control to below -100°C. The CCD characteristics are given in Table 2 along with the schematic of the CCD370 in Figure 2.

Figure 2:

CCD370 schematic on the left and in its handling jig for the SMILE program on the right.

Table 2:

CCD370 main characteristics.

Notes:

1- When operating with two adjacent phases held high. Defined as the point at which the response is non-linear. Measured using flat-field illumination.

2- Calculated with a camera bandwidth of 15 MHz predicted with single ended readout.

The detector used for the PLATO mission, CCD280, has been used to predict the CCD370 post radiation performance [3]. The results show that the CCD370 will meet the end-of-life performance when the temperature is kept below -85 °C. Figure 3 (figure 13 from [3]) shows the CTI performance post annealing.

Figure 3:

CTI performance post annealing [3].

The program is now moving to the lot acceptance testing (LAT) phase for flight model (FM) delivery.

The SMILE mission has the capability to cool the image sensor down to cryogenic temperatures during evaluation testing to correctly evaluate the CCD end-of-life performance.

3.1

Large area CMOS development from Teledyne e2v

Teledyne e2v has developed a new CIS300 family of CMOS detectors to specifically address astronomy, space, low noise and high dynamic range applications while being a platform that can be adapted with minimum risk for many other specific applications. Teledyne e2v has completed the design of the first two products from this family: CIS301 and CIS302, which is the high NIR sensitivity version of CIS301 using the HiRho technology. This platform is the results of years of R&D innovation re-using silicon proven blocks from various projects. The key innovations that will be discussed in this section are:

CIS300 a flexible large area detector platform

The CIS301 is a large area backthinned CMOS image sensor in a 3-sided close buttable package (See Figure 4 and Figure 5). It features:

Figure 4:

CIS302 wafer scale – top level layout view.

Figure 5:

CIS301/CIS302 package and focal plane array (FPA) arrangement example.

The CIS302, second product of the family, is the HiRho version of the CIS301:

Package designed to be 3-side buttable (Figure 5).

The detectors predicted performance are reported in Table 3. The family is built on a 2D stitch platform which enables different detector sizes to be manufactured with the same mask set as shown Figure 6. Further the column readout for the family is based on a 5μm pitch making the platform suitable for pixel pitches of 5μm and larger.

Table 3:

Performance CIS301 and CIS302 detectors.

Figure 6:

CIS301 and CIS302 format variant using the same mask set.

The CIS300 platform has been built on the heritage of silicon proven blocks and technologies. The low noise approach in particular was important and was addressed by 5 design considerations (represented Figure 7):

These 5 points are the focus of the next sections.

Figure 7:

CIS302 - low noise approach.

3.2

Large area with High CVF

To achieve noise floor below 2 e^-_RMS CIS300 family relies on a high gain of 80-90μV/e^- at sense node. This is higher than the typical achievable value from standard imaging process which is more around 50-60μV/e^-. In order to reach 80-90μV/e^- some specific design technics must be considered. Although several generations of detectors have achieved these high values a summary of the technics used for CIS300 is presented below.

In order to achieve 80-90μV/e^- three main considerations have been looked at:

The high CVF brings a lower sense node FWC as a consequence. It was therefore important to design a reset scheme and ADC to enable the largest possible voltage swing at the sense node by:

Although this does not impact the noise performance it helps with dynamic range by optimizing the FWC.

The first large area high CVF and low noise CMOS detector demonstrated by Teledyne e2v is the CIS113, developed as part of the TAOSII mission [4]. This was a large area CMOS detector (1920 x 4608 Pixels of 16μm square) with low noise, below 3 e^-_RMS, and a reasonable FWC of 20 ke^-. The pixel was a 5T structure similar to CIS300 pixel.

Figure 8:

CIS113 large area (pixel array of about 3.1cm x 7.4cm) and low noise CMOS detector.

The CIS113 was used in cryogenic environment which enabled the assessment of performance across a wide temperature range. The figures below shows that CVF increases (Figure 9) with lower temperature while the noise floor in electron remains constant (Figure 10). This is explained by the fact that the 1/f noise appears first as a current from the in-pixel source follower that is integrated into the column and sense node capacitances. As the temperature reduces the noise in μV increases (Figure 10) proportionally to the decrease of the sense node capacitance (or increase of the CVF) keeping the ratio of CVF increase to noise in μV constant. The implication is that the optimum sizing for the in-pixel source follower is in relation between its parasitic capacitance and the sense node targeted capacitance. Further detail can be found in [5]. Note that CIS113 is now a device in production.

Figure 9:

CIS113 CVF and Linear charge capacity versus temperature.

Figure 10:

CIS113 noise performance versus temperature: left noise in μVRMS and right in e-RMS.

Having increased the gain as much as possible (using standard design rules) within the technology and design capabilities the next step was to improve the in-pixel CVF distribution across the large pixel area. This has been achieved with the implementation of HiRho technology, which along with improving QE and MTF significantly improves the inpixel gain distribution

3.3

Enhanced sensitivity and improved in-pixel gain distribution

The sensitivity of the device is also an important characteristic of photon starved applications especially for NIR and soft X-ray missions. Teledyne e2v has already successfully transferred the CCD back thinning capability to CMOS and more recently has implemented of its HiRho CMOS technology. The pixel of the CIS300 family has been designed with this technology.

A weak point of CMOS technology is the photodiode depletion depth which is smaller in comparison to the CCD. This is due to the fact that CMOS uses lower voltages. This lack of deep depletion implies that once back thinned the total thickness cannot exceed around 10 μm without a strong MTF degradation, even when using high resistivity epitaxial material. This limits the QE in NIR. The HiRho technology addresses this dilemma. This technology consists of supplying a negative voltage, named reverse bias, to the back surface while preventing the transistor from leaking [6]. Figure 11 shows a representation where the Deep Depletion Extension (DDE) is a special implant added in the pixel to protect the in-pixel transistors from the reverse bias.

Figure 11:

HiRho – 2 pixels reverse bias in-pixel DDE protection representation.

This technology has been implemented successfully as part of a European Space Agency GSTP funded program. The device designed (CIS22) is a HiRho version of the CIS120 general multi-purpose detector, 2k x 2k, 10 μm pitch, 5T pixel with global and rolling shutter operation. This device has been selected for ESA’s Copernicus CO2M mission) [7]. The QE and MTF have been measured for two EPI thicknesses of 17 μm with -6 V reverse bias, and 33 μm with -20 V reverse bias, see Figure 12 and Figure 13. The MTF is almost a constant across the wavelengths which demonstrates full depletion, although the values are slightly lower than the perfect theoretical value and slightly lower for the 33 μm thickness compared to 17 μm. This is explained by the aspect ratio between the pixel pitch of 10 μm and the thicknesses (17 μm and 33 μm). Some electrons can escape the pixel depletion region due to lateral diffusion to be captured by a neighbouring pixel. Nevertheless, these results show an important sensitivity increase in the NIR compared to the CIS120 non-HiRho detector. The QE response of CIS220 is significantly higher at wavelengths above 700 nm and almost double from 850 nm onwards for the 33 μm thick device compared to the CIS120. Importantly MTF performance of the CIS220 is not compromised by using thicker silicon and is improved compared to CIS120. It is worth pointing out that as the QE roll off appears later, the fringing effect is reduced improving performance for narrow wavelength bandwidth applications like hyperspectral imaging or spectroscopy. This is another important key point of this technology.

Figure 12:

CIS220 HiRho QE response for two thicknesses and comparison with non-HiRho CIS120 thinned to 9μm.

Figure 13:

CIS220 HiRho MTF response for two thicknesses.

The in-pixel gain distribution of the HiRho device is also significantly improved. The CCF (Charge Conversion Factor, digital equivalent of CVF for analogue devices) has a much tighter distribution. This is key for large area devices and critical for sub electron performance. Figure 14 reports a comparison between the distribution of CCF for CIS120 (non-HiRho) and CIS220 (HiRHo with 17μm thick EPI). A substantial improvement of 2 to 3 can be observed. The two devices have been tested on the same camera using the same analysis software.

Figure 14:

HiRho impact on CCF distribution: left CIS120 (non-HiRho) and right CIS220 (HiRho).

Further CIS220 was expected to have a good Parasitic Light Sensitivity (PLS) performance as it is using thick material (17μm EPI) and it is fully depleted. The left graph Figure 15 indicates that PLS performance in percent is constant up to saturation level and after this point the PLS increases. This right graph Figure 13 shows a decrease of PLS performance with longer wavelength which is expected as the device is back illuminated and therefore at longer wavelength the electrons are generated too close to the sense node. The observation can be categorized as:

Note that CIS220 is targeting to close TRR in coming months. A campaign of radiation is planned by end 2022.

Figure 15:

CIS220 PLS perfromance versus signal level (left) and wavelength right.

3.4

Column amplifier and Ultra-Low noise in-pixel source follower:

Figure 16 is an illustration of a typical readout out digital path with a column PGA (Programmable Gain amplifier). For the CIS300 family the gains proposed varies from x 1 (bypass), x 2 to x 31. A similar approach was already used successfully on CIS124 [8]. This is a large array detector of 800 x 800 4T pixel, with low noise (3 e^-_RMS) and high frame rate (700 fps) designed for the ELT program as a wavefront sensor for ESO. Since the noise target was below 3 e^-_RMS PGA in this case had a gain of only up to x 8. However, as the CIS300 family is targeting a noise floor below 2 e^-_RMS and even sub electron in some mode the gains of the PGA needed to be increased. The choice of gains is also a function of the ADC noise floor. Here we have implemented a single slope ADC from industrial application optimized and featuring a noise floor below 100 μV_RMS. Between the PGA and ADC a correlated double sampling (CDS) circuit is used to remove KTC noise and very low frequency and very high frequency noise components as the CDS acts as a bandpass filter.

Figure 16:

Readout path with top level view of timing and noise contributions.

Figure 17 reports CIS124 noise floor versus PGA gain showing a significant noise reduction. Note that CIS124 is now in its production phase.

Figure 17:

CIS124 noise floor versus PGA gain.

To fully take advantage of the high CVF, the reduction of in-pixel gain distribution and column PGA structure it was important to have a tighter in-pixel source follower noise distribution. A new structure called ultra-low noise has been successfully experimented on silicon. Figure 18 shows a significant improvement in the noise tail. Further we can see a mean value measured at 1.6 e^-_RMS with a modest CVF of 70μV/e^-. This value is now low enough to target sub electron performance using non-destructive readout or multi-sampling technics.

Figure 18:

Performance of pixel with ultra-low noise process (in red) compared to low noise process (in blue) obtained with a CVF of 70μV/e- [9].

The CIS300 family targets a noise floor close to 1.6 e^-_RMS using high CVF, in-pixel ultra-low noise source follower with a tight distribution and a column amplifier to render the ADC readout noise negligible. The non-destructive read out or multi-sampling will further reduce the noise floor to achieve sub electron performance. These modes can be important features for applications where long integration time is used and where cosmic ray artefacts must be removed for instance. However, more work is required to choose the best option between non-destructive read out and multisampling. In CMOS technology non-destructive read out relys on building-up a voltage at the sense node. This node is not pinned and its dark current is significantly higher than the dark current of the photodiode. This might be a limitation post radiation and a multi-sampling approach with sub electron performance might be preferred in some applications.