In this work, we have studied the possibility of using a MEMS accelerometer to generate seeds for a secure cryptosystem. The noise signal generated by the accelerometer at rest has been studied and, after a post-processing process, has been used to generate the initial parameters of a stream cipher based on a piecewise linear chaotic map. The encryption algorithm has been implemented in a Xilinx Virtex 7 FPGA achieving a throughput of 200 Mbps using 390 LUTS. The resulting sequences generated by this system have been subjected to the NIST randomness tests, passing all of them, indicating that the whole encryption system is secure.
Capacitive MEMS sensors exhibit an excellent noise performance, high sensitivity and low power consumption. They offer a huge range of applications, being the accelerometer one of its main uses. In this work, we present the design of a capacitance-to-voltage converter in CMOS technology to measure the acceleration from the capacitance variations. It is based on a low-power, fully-differential transimpedance amplifier with low input impedance and a very low input noise.
This work presents a new continuous-time equalization approach to overcome the limited bandwidth of integrated CMOS photodetectors. It is based on a split-path topology that features completely decoupled controls for boosting and gain; this capability allows a better tuning of the equalizer in comparison with other architectures based on the degenerated differential pair, which is particularly helpful to achieve a proper calibration of the system. The equalizer is intended to enhance the bandwidth of CMOS standard n-well/p-bulk differential photodiodes (DPDs), which falls below 10MHz representing a bottleneck in fully integrated optoelectronic interfaces to fulfill the low-cost requirements of modern smart sensors. The proposed equalizer has been simulated in a 65nm CMOS process and biased with a single supply voltage of 1V, where the bandwidth of the DPD has been increased up to 3 GHz.
We present a new CMOS analog continuous-time equalizer that overcomes the limitations of the most widely used continuous-time equalizer, the degenerated differential pair. The equalizer has been proved for multi-gigabit short-range applications targeting up to 2 Gb/s through a 50-m SI-POF. The prototype consumes 2.7 mW for a 1-V supply voltage.